Abstract: A programmable, special-purpose, pipeline processing system for processing dynamic programming algorithms. The pipeline processing system includes a plurality of accelerator chips coupled in series. The first and last accelerator chips are coupled to interface logic. Each of the accelerator chips includes an instruction processor; a plurality of pipeline processor segments coupled in series. Each of the pipeline processor segments includes a plurality of pipeline processors coupled in series. Each of the pipeline processors has an output and has as one input an output from a preceding pipeline processor and, as a set of second inputs, a corresponding set of outputs from the instruction processor. Also provided is a result processor having an output, and having as one input, an output from a prior result processor, and, as a second input, the output from one of the plurality of pipeline processors.