Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e.g., VCC) to a voltage that is higher in potential (e.g., VCCP) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e.g., VBB) that is lower in voltage than the ground voltage.

Abstract: A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e.g., VCC) to a voltage that is higher in potential (e.g., VCCP) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e.g., VBB) that is lower in voltage than the ground voltage.

Abstract: A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

Abstract: A charge pump includes a pair of capacitors each having a first terminal coupled to a pumped node. A charge voltage is initially applied to the pumped node to charge the capacitors. A second terminal of the first capacitor is then pumped to increase the voltage at the pumped node, with the charge of the first capacitor being shared with the second capacitor. The second terminal of the second capacitor is then pumped to again increase the voltage at the pumped node. The pumped node is then coupled to an output terminal.

Abstract: A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.

Abstract: An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: In a fuse programmable voltage generator providing an optimal internal voltage VCCINT, a counter outputs various values to a voltage down comparator to output corresponding internal voltages VCCINT until a desired voltage is obtained. Once the desired internal voltage VCCINT is determined, the counter is disabled and a fuse circuit is configured to substantially maintain the output of the desired internal voltage VCCINT.

Abstract: A high efficiency charge pump for low and wide voltage ranges. The charge pump includes main and secondary charge pumps, the secondary charge pump is employed to avoid the Vt.sub.N drop that the main charge pump exhibits. The secondary charge pump allows the main charge pump to pump to a theoretical maximum of 2 VCC, while maintaining an efficiency close to 40%.

Abstract: A negative charge pump circuit for low voltage and wide voltage range applications. The charge pump includes two single-stage p-type pumps. One of the pumps is used to charge a circuit node down to a threshold voltage .vertline.Vt.sub.p .vertline. less than a desired voltage. When used in such a way, the other pump will charge a substrate to a full -VCC.

Abstract: A substrate bias generator avoids using a free-running oscillator and thereby saves power in the standby mode. A clock enable signal from a regulator sets a latch in a self-timed clock circuit. The latch setting initiates a first group of clock signals (that are used by a pump circuit for pumping), at the end of which the latch is reset but concomitantly an input circuit to the latch is disabled from recognizing a new pump signal. Resetting the latch causes the clock circuit to generate a second group of clock signals used in the charge pump to prepare fully for the next demand for pumping. At the end of the second group of clock signals, a full cycle of clocks has been completed in a self-timed manner, and the input circuit to the latch is reenabled to recognize a subsequent pump signal.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method :for refreshing a DRAM are also disclosed.