Patents by Inventor Michael V. Leoni

Michael V. Leoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6921979
    Abstract: A bond pad (200) has a first wire bond region (202) and a second wire bond region (204). In one embodiment, the first wire bond region (202) extends over a passivation layer (18). In an alternate embodiment, a bond pad (300) has a probe region (302), a first wire bond region (304), and a second wire bond region (306). In one embodiment, the probe region (302) and the wire bond region (304) extend over a passivation layer (18). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Susan H. Downey, Peter R. Harper, Kevin Hess, Michael V. Leoni, Tu-Anh Tran
  • Publication number: 20030173668
    Abstract: A bond pad (200) has a first wire bond region (202) and a second wire bond region (204). In one embodiment, the first wire bond region (202) extends over a passivation layer (18). In an alternate embodiment, a bond pad (300) has a probe region (302), a first wire bond region (304), and a second wire bond region (306). In one embodiment, the probe region (302) and the wire bond region (304) extend over a passivation layer (18). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.
    Type: Application
    Filed: November 26, 2002
    Publication date: September 18, 2003
    Inventors: Susan H. Downey, Peter R. Harper, Kevin Hess, Michael V. Leoni, Tu-Anh Tran