Abstract: Methods for bonding a donor wafer to a receiver element and transferring a lamina from the donor wafer to the receiver element are disclosed herein. The donor wafer may be, for example, a monocrystalline silicon wafer with a thickness of from about 300 microns to about 1000 microns, and the lamina may be may be less than 100 microns thick. The receiver element may be composed of, for example, metal or glass, and the receiver element may have dissimilar thermal expansion properties from the lamina. Although the lamina and the receiver element may have dissimilar thermal expansion properties, the methods disclosed herein maintain the integrity of the bond between the lamina and the receiver element.

Abstract: Methods for bonding a donor wafer to a receiver element and transferring a lamina from the donor wafer to the receiver element are disclosed herein. The donor wafer may be, for example, a monocrystalline silicon wafer with a thickness of from about 300 microns to about 1000 microns, and the lamina may be may be less than 100 microns thick. The receiver element may be composed of, for example, metal or glass, and the receiver element may have dissimilar thermal expansion properties from the lamina. Although the lamina and the receiver element may have dissimilar thermal expansion properties, the methods disclosed herein maintain the integrity of the bond between the lamina and the receiver element.

Abstract: A method for forming a contact in a three dimensional monolithic memory is disclosed. In a preferred embodiment, the method comprises depositing a conductive layer over and in contact with a plurality of antifuses, wherein said antifuses are part of a story of active devices formed above a substrate; patterning and etching said conductive layer and insulating dielectric to form a contact void; and filling the contact void, wherein the conductive layer does not comprise silicon.

Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.