Abstract: Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g.

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

Abstract: An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

Abstract: An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

Abstract: Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.

Abstract: Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.

Abstract: In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.

Abstract: An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a clock signal for clocked data based on a local clock signal. In some embodiments, the local clock signal may also be used to transmit the clocked data.

Abstract: A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.

Abstract: A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.

Abstract: A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.

Abstract: A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.

Abstract: An apparatus and method for recovering a clock signal from a Coded Marked Inversion (CMI) encoded signal. A delay and divide circuit receives an incoming CMI encoded signal and produces a signal that has transitions corresponding to the bit boundaries of the CMI signal. This signal is then passed through a clock recovery loop (i.e., a phase-locked loop) to synchronize a clock signal with a CMI signal. The clock recovery loop further includes a delay circuit that adjusts the timing of the feedback signal such that it matches the delay of the CMI signal that occurs as the CMI signal passes through the delay and divide circuit. Accordingly, the circuit adjusts the timing of the recovered clock signal until it matches the clocking of the incoming CMI signal.