Patents by Inventor Michael W. Beattie

Michael W. Beattie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7827514
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Grant
    Filed: September 3, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Beattie, Anirudh Devgan, Byron L. Krauter, Hui Zheng
  • Patent number: 7590952
    Abstract: A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Beattie, Kevin Beattie, legal representative, Byron L. Krauter, Hui Zheng
  • Publication number: 20080300848
    Abstract: A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 4, 2008
    Inventors: Michael W. Beattie, Byron L. Krauter, Hui Zheng
  • Publication number: 20080127010
    Abstract: A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Inventors: Michael W. Beattie, Kevin Beattie, Byron L. Krauter, Hui Zheng
  • Patent number: 7302661
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Beattie, Anirudh Devgan, Byron L. Krauter, Hui Zheng
  • Patent number: 7096174
    Abstract: Systems, methods and computer program products create an equivalent circuit of electric and/or electronic circuit components, by identifying groups of components and hierarchically modeling aggregate interactions among the groups of components, to create increasingly higher level circuit models, until the equivalent circuit for the components is produced. Hierarchical modeling is provided by defining global components that reflect aggregate parameters of the groups of components and modeling the aggregate interaction among the groups of components as interactions among the global components. Moreover, next higher level global components also are defined that reflect aggregate parameters of at least some of the global components, and the aggregate interaction among the groups of components is modeled as interactions among the next higher level global components.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: August 22, 2006
    Assignee: Carnegie Mellon University
    Inventors: Michael W. Beattie, Lawrence T. Pileggi
  • Patent number: 6820245
    Abstract: Inductive effects in an integrated circuit device and/or system are modeled by partitioning the integrated circuit device and/or system into multiple windows or portions and determining a first localized inductance matrix for a first portion of the circuit and/or system and a second localized inductance matrix for a second portion of the circuit and/or system. The first and second localized inductance matrices are solved to obtain first and second localized susceptance vectors. The first and second localized susceptance vectors may be combined to form a susceptance matrix, which may be used directly in a susceptance-based simulator, or inverted to obtain a sparser inductance matrix that is representative of the inductive couplings in the entire integrated circuit device and/or system.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: November 16, 2004
    Assignee: Carnegie Mellon University
    Inventors: Michael W. Beattie, Lawrence T. Pileggi
  • Publication number: 20030177458
    Abstract: Inductive effects in an integrated circuit device and/or system are modeled by partitioning the integrated circuit device and/or system into multiple windows or portions and determining a first localized inductance matrix for a first portion of the circuit and/or system and a second localized inductance matrix for a second portion of the circuit and/or system. The first and second localized inductance matrices are solved to obtain first and second localized susceptance vectors. The first and second localized susceptance vectors may be combined to form a susceptance matrix, which may be used directly in a susceptance-based simulator, or inverted to obtain a sparser inductance matrix that is representative of the inductive couplings in the entire integrated circuit device and/or system.
    Type: Application
    Filed: March 12, 2002
    Publication date: September 18, 2003
    Inventors: Michael W. Beattie, Lawrence T. Pileggi
  • Publication number: 20030069722
    Abstract: Systems, methods and computer program products create an equivalent circuit of electric and/or electronic circuit components, by identifying groups of components and hierarchically modeling aggregate interactions among the groups of components, to create increasingly higher level circuit models, until the equivalent circuit for the components is produced. Hierarchical modeling is provided by defining global components that reflect aggregate parameters of the groups of components and modeling the aggregate interaction among the groups of components as interactions among the global components. Moreover, next higher level global components also are defined that reflect aggregate parameters of at least some of the global components, and the aggregate interaction among the groups of components is modeled as interactions among the next higher level global components.
    Type: Application
    Filed: July 17, 2001
    Publication date: April 10, 2003
    Inventors: Michael W. Beattie, Lawrence T. Pileggi