Patents by Inventor Michael W. Bruns
Michael W. Bruns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11849130Abstract: Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: GrantFiled: April 29, 2022Date of Patent: December 19, 2023Assignee: Coherent Logix, IncorporatedInventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Patent number: 11544895Abstract: Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.Type: GrantFiled: September 25, 2019Date of Patent: January 3, 2023Assignee: Coherent Logix, Inc.Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah
-
Patent number: 11483580Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficiently and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.Type: GrantFiled: June 11, 2013Date of Patent: October 25, 2022Assignee: Coherent Logix, IncorporatedInventors: Michael W. Bruns, Michael B. Solka, Carl S. Dobbs, Martin A. Hunt, Michael B. Doerr, Tommy K. Eng
-
Publication number: 20220264130Abstract: Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: ApplicationFiled: April 29, 2022Publication date: August 18, 2022Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Patent number: 11323729Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: GrantFiled: December 21, 2020Date of Patent: May 3, 2022Assignee: Coherent Logix, IncorporatedInventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Publication number: 20210152839Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: ApplicationFiled: December 21, 2020Publication date: May 20, 2021Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Patent number: 10873754Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: GrantFiled: December 11, 2018Date of Patent: December 22, 2020Assignee: Coherent Logix, IncorporatedInventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Publication number: 20200098164Abstract: Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.Type: ApplicationFiled: September 25, 2019Publication date: March 26, 2020Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah
-
Publication number: 20190182495Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.Type: ApplicationFiled: December 11, 2018Publication date: June 13, 2019Inventors: Michael W. Bruns, Michael A. Hunt, Manjunath H. Siddaiah, John C. Sievers
-
Publication number: 20130343450Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficient and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.Type: ApplicationFiled: June 11, 2013Publication date: December 26, 2013Inventors: Michael B. Solka, Michael B. Doerr, Carl S. Dobbs, Michael W. Bruns
-
Patent number: 5982249Abstract: A reduced crosstalk microstrip transmission-line has a plurality of microstrips sandwiched between a lower base dielectric layer of flexible circuit material and an upper coverlay with higher permittivity and of different flexible circuit material than the base dielectric layer. With the higher permittivity of the coverlay, the thickness of the coverlay is selected such that the microstrip transmission-line retains practical flexibility and far-end crosstalk to a first neighboring microstrip from a driving channel is zero.Type: GrantFiled: March 18, 1998Date of Patent: November 9, 1999Assignee: Tektronix, Inc.Inventor: Michael W. Bruns