Abstract: A method is provided for extracting overlay information from a target of an integrated circuit wafer wherein the first-level target has features wh are optically concealed by an overlying opaque planarized film. The target employed has an architecture including a resist feature on the planarized film and an embedded electron backscattering target feature disposed beneath the planarized film. This target is scanned with an electron bean of an energy sufficiently high (e.g., at least 11 keV) to penetrate the planarized film, be backscattered by the backscattered feature and return through the planarized film or through the planarized film and the resist feature. Electrons backscattered from the conductive first-level target feature through the resist feature are detected and a signal profile is generated based thereon. This signal profile is analyzed to extract overlay information.

Abstract: An improved test structure for measurement of width of conductive lines formed on substrates as performed in semiconductor fabrication, and an improved reference grid for calibrating instruments for such measurements, is formed from a monocrystalline starting material, having an insulative layer formed beneath its surface by ion implantation or the equivalent, leaving a monocrystalline layer on the surface. The monocrystalline surface layer is then processed by preferential etching to accurately define components of the test structure. The substrate can be removed from the rear side of the insulative layer to form a transparent window, such that the test structure can be inspected by transmissive-optical techniques. Measurements made using electrical and optical techniques can be correlated with other measurements, including measurements made using scanning probe microscopy.

Abstract: A test structure for submicrometer metrology as used in integrated circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads.

Abstract: Imaging instruments for inspecting products, such as semiconductor chips, e calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument, and by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements are made by forcing a current between a plurality of spaced reference features and a pair of underlying conductors. Conductive connectors formed in vias in an insulating layer overlying the pair of conductors and individually connected to a respective conductive element formed on the insulating layer are each spaced at progressively greater distances relative to the centerline of the space between the pair of conductors, such that a null-overlay element may be identified.

Abstract: An improved test structure for measurement of width of conductive lines formed on substrates as performed in semiconductor fabrication, and for calibrating instruments for such measurements, is formed from a monocrystalline starting material, having an insulative layer formed beneath its surface by ion implantation or the equivalent, leaving a monocrystalline layer on the surface. The monocrystalline surface layer is then processed by preferential etching to accurately define components of the test structure. The substrate can be removed from the rear side of the insulative layer to form a transparent window, such that the test structure can be inspected by transmissive-optical techniques. Measurements made using electrical and optical techniques can be correlated with other measurements, including measurements made using scanning probe microscopy.

Abstract: Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements may be made by forcing a current between a plurality of spaced reference features and an underlying conductor, or may be made by capacitive, conductive, magnetic, or impedance-measuring techniques. Capacitive techniques may also be used to detect features not susceptible of resistance measurement, such as dielectric or insulative materials, or metallic structures not accessible for forcing a current therethrough.

Abstract: A test structure for submicrometer metrology as used in integral circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads.

Abstract: A silicon-based monolithic microwave integrated circuit architecture is described. This architecture, called MICROX.TM., is a combination of silicon material growth and wafer processing technologies. A wafer is fabricated using a substrate of high resistivity silicon material. An insulating layer is formed in the wafer below the surface area of active silicon, preferably using the SIMOX process. A monolithic circuit is fabricated on the wafer. A ground plane electrode is formed on the back of the wafer. Direct current and rf capacitive losses under microstrip interconnections and transistor source and drain electrodes are thereby minimized. Reduction in the resistivity of the substrate material as a result of CMOS processing can be minimized by maintaining a shielding layer over the bottom surface of the wafer. Microstrip and airbridge connectors, salicide processing and nitride side wall spacing can be used to further enhance device performance.

Abstract: A prepatterned potentiometer precursor includes a precursor substrate; and at least two spaced apart potentiometer precursor patterns on the substrate, each potentiometer precursor pattern including a bridge, two substantially similar end taps transverse to and extending from the bridge, and a center tap transverse to and extending from the bridge and centrally disposed between the end taps wherein the center taps of the bridges are substantially parallel to each other and are substantially wider than the end taps. A method of determining the distance between test features of test patterns on a test piece includes preparing a precursor substrate including at least two electrically conducting spaced apart potentiometer precursor patterns, each potentiometer precursor pattern including a bridge, two substantially similar end taps transverse to and extending from the bridge, and a center tap transverse to and extending from the bridge and centrally disposed between the end taps.

Abstract: A system which samples and records the locations of opaque particles accumulating on a surface. The system represents graphically the geometrical distributions of the particles through an integral electronic hardware/software subsystem. The key component is a radiant energy sensitive sensor which produces the sampling surface. The sensor is exposed to a constant level of radiant energy. Opaque particles becoming resident upon the sensor surface inhibit sensitization of the surface by the radiant energy and thereby indicates the presence and location of the particle. Embodiments of the sensor include charge coupled devices (CCDs), photodiode arrays, intrinsic or extrinsic "bulk" material, and optically- or UV-erasable memories.

Abstract: A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input.A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes.

Abstract: A thin film electroluminescent edge emitter assembly includes a substrate layer having a configuration to define at least one lateral edge surface and at least one integrated circuit formed therein. The integrated circuit has an input for receiving logic signals, and has an excitation voltage input and a plurality of output leads. The output leads form control electrodes each having an end portion terminating at the substrate lateral edge surface. The integrated circuit is operable to provide an excitation voltage to selected control electrodes in response to preselected logic signals provided to the integrated circuit at the logic signal input. A laminar arrangement formed from a first dielectric layer, a second dielectric layer, a phosphor layer interposed between the first and second dielectric layers and a common electrode layer is disposed on the end portions of the control electrodes.

Abstract: An improved phased-array active antenna transmit-receive means utilizing a multiplicity of individual transmit-receive cells positioned in an array format upon a common wafer of semiconductor material. Each transmit-receiver cell, comprises a multiplicity of redundant, integrated circuit, electronic devices implanted upon the common semiconductor substrate. The transmit-receive cells utilize novel mitered mechanical switches to permanently interconnect individual electronic devices into either transmit or receive circuits during the fabrication and test of the transmit-receive cells. Radio frequency and direct current input and output vias formed from a novel metal evaporation technique connect the devices upon the surface of the common semiconductor wafer to underlying, insulated direct current distribution circuits and a radio frequency manifold.

Abstract: An improved phased-array active antenna transmit-receive means utilizing a multiplicity of individual transmit-receive cells positioned in an array format upon a common wafer of semiconductor material. Each transmit-receive cell, comprises a multiplicity of redundant, integrated circuit, electronic devices implanted upon the common semiconductor substrate. The transmit-receive cells utilize novel mitered mechanical switches to permanently interconnect individual electronic devices into either transmit or receive circuits during the fabrication and test of the transmit-receive cells. Radio frequency and direct current input and output vias formed from a novel metal evaporation technique connect the devices upon the surface of the common semiconductor wafer to underlying, insulated direct current distribution circuits and a radio frequency manifold.

Abstract: An improved phased-array active antenna transmit-receive means utilizing a multiplicity of individual transmit-receive cells positioned in an array format upon a common wafer of semiconductor material. Each transmit-receive cell, comprises a multiplicity of redundant, integrated circuit, electronic devices implanted upon the common semiconductor substrate. The transmit-receive cells utilize novel mitered mechanical switches to permanently interconnect individual electronic devices into either transmit or receive circuits during the fabrication and test of the transmit-receive cells. Radio frequency and direct current input and output vias formed from a novel metal evaportion technique connect the devices upon the surface of the common semiconductor wafer to underlying, insulated direct current distribution circuits and a radio frequency manifold.

Abstract: Conductivity modulation states in a first component of a power integrated circuit are dynamically isolated from a second component of the integrated circuit having at least one common active region with the first component by selective irradiation of portions of the common regions between the components. Preferably the irradiation is accomplished by masking the component portions of the body with a radiation shield and irradiating selected portions of the common active regions between the component portions with a suitable radiation source. The radiation source is preferably an electron beam of an energy level between about 1 and 3 Mev, preferably where the irradiation is carried to a dosage between 1.times.10.sup.13 and 1.times.10.sup.15 e/cm.sup.2 and most desirably between 4.times.10.sup.13 and 2.times.10.sup.14 e/cm.sup.2. New high speed bilateral thyristors, reverse switching rectifiers and reverse conducting thyristors are also provided.

Abstract: A light activated semiconductor switch comprises a light source for activating a light activated semiconductor device. A remote controllable light deflecting device is interposed between the light activated device and the light source for directing the light source onto the light activated device at a specified time in the rise time of the light source in response to a signal in order to decrease the switching time of the light activated device.

Abstract: An improved method of fabricating apertured deposition masks is disclosed, with the masks being used in the fabrication of thin film deposited electronic components such as transistors. The masks comprise a core portion with a metal layer provided on a relief side of the core and a metal layer provided on the defining side of the core. The relief side metal layer and the core of the mask are further resist delineated, selectively plated and etched differentially providing a mask preform in which the defining side metal layer is left intact. A narrow width radiation beam is then directed upon closely spaced portions of the defining side metal layer to selectively cut through the defining side metal layer providing the desired space apertures separated by a narrow bridge portion of the defining side metal layer.

Abstract: A thyristor is provided with a low forward voltage drop (V.sub.f) while providing a typical gate current to trigger (I.sub.g). The working point in the cathode-base region of the thyristor has an impurity concentration less than 5 .times. 10.sup.15 and preferably less than 1 .times. 10.sup.15 per cm.sup.3. The gating portion of the device is selectively irradiated, preferably with electron radiation, to maintain the gate current. The forward blocking voltage (V.sub.BO) and rate of rise of application of forward voltage (dV/dt) of the thyristor may also be maintained at typical values by a fine shunt pattern and/or doping of the shunt portions.

Abstract: A thyristor is provided with a low forward voltage drop (V.sub.f) while providing a typical gate current to trigger (I.sub.g). The working point in the cathode-base region of the thyristor has an impurity concentration less than 5 .times. 10.sup.15 and preferably less than 1 .times. 10.sup.15 per cm.sup.3. The gating portion of the device is selectively irradiated, preferably with electron radiation, to maintain the gate current. The forward blocking voltage (V.sub.BO) and rate of rise of application of forward voltage (dV/dt) of the thyristor may also be maintained at typical values by a fine shunt pattern and/or doping of the shunt portions.