Abstract: Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net names with unrelated unique identifiers prior to transferring the design views as part of a simulation model of a circuit design, and consequently avoiding unauthorized use of that information. The method for encoding signal names in different design views of an IC design includes providing a list of names contained in a plurality of design databases, changing each name in the list of names to a protected name, and substituting each changed name with an associated protected name in each design view database.

Abstract: A method and apparatus for interconnecting circuit portions (12, 14, 16, 18, 20) within a data processing system (10) using a master/slave interfaces (30–37, 134) which may be configured by way of configuration registers (21–28, 156, 100). External address generation circuitry (140) and internal address generation circuitry (142) may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g. 20) may have a plurality of interfaces (37, 134) which may operate as a slave interface (e.g. 134) or as a master interface (e.g. 37). A same master/slave interface structure and protocol (e.g. 30, 140, 142, 144, 28, 152) may be duplicated and individually configured to be used to communicate among all of the circuit portions (12, 14, 16, 18, 20) within a data processing system (10).

Abstract: A method and apparatus for interconnecting circuit portions (12, 14, 16, 18, 20) within a data processing system (10) using a master/slave interfaces (30-37, 134) which may be configured by way of configuration registers (21-28, 156, 100). External address generation circuitry (140) and internal address generation circuitry (142) may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g. 20) may have a plurality of interfaces (37, 134) which may operate as a slave interface (e.g. 134) or as a master interface (e.g. 37). A same master/slave interface structure and protocol (e.g. 30, 140, 142, 144, 28, 152) may be duplicated and individually configured to be used to communicate among all of the circuit portions (12, 14, 16, 18, 20) within a data processing system (10).