Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Abstract: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

Abstract: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Abstract: Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.

Abstract: Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.