Abstract: A redox flow battery may include: a positive half-cell comprising a catholyte; a negative half-cell comprising an anolyte; and an ion permeable membrane, wherein the ion permeable membrane separates the catholyte and the anolyte, and wherein the catholyte, the anolyte, or both comprise a low-transition temperature material comprising: a redox-active phase; and an ionically conducting organic salt.

Abstract: A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Abstract: Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.

Abstract: Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.

Abstract: A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Abstract: An anti-counterfeiting technique presents, to a test thermoreflective mark at a first temperature, a first electromagnetic wave. A first test reflective profile for the test thermoreflective mark associated with the first temperature is recorded. A second electromagnetic wave is presented to the test thermoreflective mark at a second temperature. A second test reflective profile for the test thermoreflective mark associated with the second temperature is recorded. The first test reflective profile is compared with a first control reflective profile that is associated with a genuine thermoreflective mark. The second test reflective profile is compared with a second control reflective profile that is associated with the genuine thermoreflective mark.

Abstract: Some embodiments of the inventive subject matter include a computer program product for validating a test thermoreflective mark. The computer program product can include computer usable program code configured to control a temperature regulation unit configured to govern a temperature of a thermoreflective mark. The computer usable program code can be further configured to control an electromagnetic waver emitter to present at a first temperature, a first electromagnetic wave. The computer usable program code can be further configured to record a first reflective profile. The computer usable program code can be further configured to control the electromagnetic wave emitter to present at a second temperature, a second electromagnetic wave. The computer usable program code can be further configured to record a second reflective profile. The computer usable code can be further configured to validate the thermoreflective mark based on the first reflective profile and the second reflective profile.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

Abstract: An anti-counterfeiting technique presents, to a test thermoreflective mark at a first temperature, a first electromagnetic wave. A first test reflective profile for the test thermoreflective mark associated with the first temperature is recorded. A second electromagnetic wave is presented to the test thermoreflective mark at a second temperature. A second test reflective profile for the test thermoreflective mark associated with the second temperature is recorded. The first test reflective profile is compared with a first control reflective profile that is associated with a genuine thermoreflective mark. The second test reflective profile is compared with a second control reflective profile that is associated with the genuine thermoreflective mark.

Abstract: Some embodiments of the inventive subject matter include a computer program product for validating a test thermoreflective mark. The computer program product can include computer usable program code configured to control a temperature regulation unit configured to govern a temperature of a thermoreflective mark. The computer usable program code can be further configured to control an electromagnetic waver emitter to present at a first temperature, a first electromagnetic wave. The computer usable program code can be further configured to record a first reflective profile. The computer usable program code can be further configured to control the electromagnetic wave emitter to present at a second temperature, a second electromagnetic wave. The computer usable program code can be further configured to record a second reflective profile. The computer usable code can be further configured to validate the thermoreflective mark based on the first reflective profile and the second reflective profile.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells. Each SRAM cell may further include a first and a second CMOS inverter that are cross-coupled. The first and second CMOS inverters may each have a first switch and a second switch. The SRAM device may also include a reset circuit. The reset circuit may be coupled to a first node of the first switch of the first CMOS inverter. The reset circuit may drive the first CMOS inverter to output a logical high signal in a reset mode.

Abstract: A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.

Abstract: Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.