Patents by Inventor Michael W. J. Hordijk

Michael W. J. Hordijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storing data to multi-chip low-latency random read memory device using non-aligned striping
    Patent number: 8086914
    Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 27, 2011
    Assignee: NetApp. Inc.
    Inventors: Jeffrey S. Kimmel, Rajesh Sundaram, George Totolos, Jr., Michael W. J. Hordijk
  • STORING DATA TO MULTI-CHIP LOW-LATENCY RANDOM READ MEMORY DEVICE USING NON-ALIGNED STRIPING
    Publication number: 20110196905
    Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Inventors: Jeffrey S. Kimmel, Rajesh Sundaram, George Totolos, JR., Michael W.J. Hordijk
  • Storing data to multi-chip low-latency random read memory device using non-aligned striping
    Patent number: 7945822
    Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: May 17, 2011
    Assignee: NetApp, Inc.
    Inventors: Jeffrey S. Kimmel, Rajesh Sundaram, George Totolos, Jr., Michael W. J. Hordijk