Patents by Inventor Michael W. Konevecki
Michael W. Konevecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8913417Abstract: A memory cell is provided that includes a steering element, a reversible resistance-switching element coupled to the steering element and a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element. The reversible resistance-switching element includes tantalum, and is formed using a selective deposition process. Numerous other aspects are provided.Type: GrantFiled: July 24, 2012Date of Patent: December 16, 2014Assignee: SanDisk 3D LLCInventors: April Schricker, Brad Herner, Michael W. Konevecki
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Patent number: 8759176Abstract: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.Type: GrantFiled: April 10, 2009Date of Patent: June 24, 2014Assignee: SanDisk 3D LLCInventors: Usha Raghuram, Michael W. Konevecki
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Patent number: 8722518Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.Type: GrantFiled: May 9, 2013Date of Patent: May 13, 2014Assignee: SanDisk 3D LLCInventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
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Publication number: 20130244395Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: SanDisk 3D LLCInventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
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Publication number: 20120286233Abstract: A memory cell is provided that includes a steering element, a reversible resistance-switching element coupled to the steering element and a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element. The reversible resistance-switching element includes tantalum, and is formed using a selective deposition process. Numerous other aspects are provided.Type: ApplicationFiled: July 24, 2012Publication date: November 15, 2012Inventors: April Schricker, Brad Herner, Michael W. Konevecki
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Patent number: 8298931Abstract: A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 ?m. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.Type: GrantFiled: September 28, 2007Date of Patent: October 30, 2012Assignee: SanDisk 3D LLCInventors: Usha Raghuram, Michael W. Konevecki
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Patent number: 8233308Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.Type: GrantFiled: June 29, 2007Date of Patent: July 31, 2012Assignee: SanDisk 3D LLCInventors: April Schricker, Brad Herner, Michael W. Konevecki
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Patent number: 7994068Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.Type: GrantFiled: March 30, 2010Date of Patent: August 9, 2011Assignee: SanDisk 3D LLCInventors: Steven J. Radigan, Michael W. Konevecki
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Patent number: 7955515Abstract: A method of plasma etching transition metal oxide thin films using carbon monoxide as the primary source gas. This permits carbonyl chemistries to be used at ambient temperature, without heating.Type: GrantFiled: March 1, 2007Date of Patent: June 7, 2011Assignee: SanDisk 3D LLCInventors: Usha Raghuram, Michael W. Konevecki
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Patent number: 7915164Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: GrantFiled: October 4, 2010Date of Patent: March 29, 2011Assignee: SanDisk 3D LLCInventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Patent number: 7915163Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: GrantFiled: June 22, 2009Date of Patent: March 29, 2011Assignee: SanDisk 3D LLCInventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Publication number: 20110021019Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: ApplicationFiled: October 4, 2010Publication date: January 27, 2011Inventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Patent number: 7846785Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.Type: GrantFiled: June 29, 2007Date of Patent: December 7, 2010Assignee: SanDisk 3D LLCInventors: April Schricker, Brad Herner, Michael W. Konevecki
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Publication number: 20100243602Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Inventors: Yung-Tin Chen, Steven J. Radigan, Paul Poon, Michael W. Konevecki
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Patent number: 7794921Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.Type: GrantFiled: December 30, 2006Date of Patent: September 14, 2010Assignee: Sandisk CorporationInventors: Yung-Tin Chen, Steven J. Radigan, Paul Poon, Michael W. Konevecki
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Publication number: 20100184259Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.Type: ApplicationFiled: March 30, 2010Publication date: July 22, 2010Inventors: Steven J. Radigan, Michael W. Konevecki
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Patent number: 7718546Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.Type: GrantFiled: June 27, 2007Date of Patent: May 18, 2010Assignee: Sandisk 3D LLCInventors: Steven J. Radigan, Michael W. Konevecki
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Publication number: 20090273022Abstract: A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: SanDisk 3D LLCInventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
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Publication number: 20090258462Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: ApplicationFiled: June 22, 2009Publication date: October 15, 2009Inventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Publication number: 20090224244Abstract: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.Type: ApplicationFiled: April 10, 2009Publication date: September 10, 2009Applicant: SANDISK 3D LLCInventors: Usha Raghuram, Michael W. Konevecki