Patents by Inventor Michael W. Lane
Michael W. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8803318Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.Type: GrantFiled: March 28, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Deepak Kulkarni, Michael W. Lane, Satyanayana V. Nitta, Shom Ponoth
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Publication number: 20130207263Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.Type: ApplicationFiled: March 28, 2013Publication date: August 15, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deepak Kulkarni, Michael W. Lane, Satyanayana V. Nitta, Shom Ponoth
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Patent number: 8440505Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.Type: GrantFiled: January 28, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Deepak Kulkarni, Michael W. Lane, Satyanarayana V. Nitta, Shom Ponoth
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Patent number: 8343868Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: GrantFiled: January 12, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 8129286Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: June 16, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures
Patent number: 8076756Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: February 19, 2011Date of Patent: December 13, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES
Publication number: 20110140245Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: February 19, 2011Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL W. LANE, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D.W. Melville -
Patent number: 7955955Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: May 10, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville
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Publication number: 20110111590Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: ApplicationFiled: January 12, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7892940Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: September 6, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7847402Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.Type: GrantFiled: February 20, 2007Date of Patent: December 7, 2010Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd, Samsung Electronics Co., LtdInventors: Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae H. Kim, Michael W. Lane, Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Johnny Widodo
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Patent number: 7820559Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: June 23, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20100187689Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.Type: ApplicationFiled: January 28, 2010Publication date: July 29, 2010Applicant: International Business Machines CorporationInventors: Deepak Kulkarni, Michael W. Lane, Satyanarayana V. Nitta, Shom Ponoth
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Patent number: 7592685Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: GrantFiled: August 31, 2007Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7573130Abstract: The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.Type: GrantFiled: January 22, 2009Date of Patent: August 11, 2009Assignee: Internatonal Business Machines CorporationInventors: Thomas M Shaw, Michael W Lane, Xio Hu Liu, Griselda Bonilla, James P Doyle, Howard S Landis, Eric G Liniger
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Patent number: 7517790Abstract: A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.Type: GrantFiled: February 8, 2005Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen M. Gates, Michael W. Lane, Eric G. Liniger
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Patent number: 7491578Abstract: The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.Type: GrantFiled: April 2, 2008Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Thomas M Shaw, Michael W Lane, Xio Hu Liu, Griselda Bonilla, James P Doyle, Howard S Landis, Eric G Liniger
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INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
Publication number: 20080277765Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
Publication number: 20080254630Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: June 16, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. EDELSTEIN, Matthew E. Colburn, Edward C. Cooney, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20080254643Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang