Patents by Inventor Michael W. LeBeane

Michael W. LeBeane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180107627
    Abstract: Methods, devices, and systems for transmitting data over a computer communications network are disclosed. A queue of communications commands can be pre-generated using a central processing unit (CPU) and stored in a device memory of a network interface controller (NIC). Thereafter, if a graphics processing unit (GPU) has data to communicate to a remote GPU, it can store the data in a send buffer, where the location in the buffer is pointed to by a pre-generated command. The GPU can then signal to the interface device that the data is ready, triggering execution of the pre-generated command to send the data.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Steven K. Reinhardt
  • Publication number: 20180081715
    Abstract: Techniques for scheduling processing tasks in a device having multiple computing elements are disclosed. A network interface controller of the device receives processing tasks, for execution on the computing elements, from a network that is external to the device. The network interface controller schedules the tasks for execution on the computing devices based on policy data available to the network interface controller. A scheduler within the network interface controller, which can be implemented as a standalone processing unit (such as a microcontroller, a programmable processing core, or an application specific integrated circuit), performs such scheduling, thereby freeing the central processing unit of the device from the burden of performing scheduling operations. The scheduler schedules the tasks according to any technically feasible scheduling technique.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Abhisek Pan, Steven K. Reinhardt
  • Publication number: 20170083382
    Abstract: First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. The first processor core is configured to selectively steal a task that was previously scheduled for execution by the second processor core based on additional power consumption incurred by migrating the task from the second processor core to the first processor core.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Michael W. LeBeane, Deepak Majeti, Mauricio Breternitz