Abstract: A system and a method using a computer for performing a boolean operation on bit strings to form a resultant bit string. Each such bit string is divided into input bit slices. The resultant bit string is divided into a resultant bit slices. An action is determined according to the boolean operation based on a first such input bit slice from a first such bit string and on a second such input bit slice from a second such bit string. The input bit slice with a longer bit length is selected from between the first input bit slice and the second input bit slice. The longer input bit slice and a plurality of the input bit slices in the bit string having the input bit slice with a shorter bit length are processed according to the determined action for up to a number of bits in at least one such bit string equaling the longer bit length to form at least one such resultant bit slice.

Abstract: A method of processing bit vectors or raw bit strings wherein the bit vectors or raw bit strings are input to a binary tree structure of processing elements. Each processing element performs a boolean "OR" operation on a pair of inputs to produce an output stream of compressed bit string fragments. Processing takes place according to dataflow principles, wherein the processing element is activated when data is available at its inputs. The output compressed bit string fragments are buffered in a FIFO before being input to another processing element at a lower level of the binary tree. A resultant bit vector or raw bit string is output from the processing element representing the root node of the binary tree. The resultant bit vector or raw bit string is a representation of the result of the boolean "OR" of all inputs.

Abstract: An embodiment of the present invention is a memory management system. A storage device is organized into at least one file comprising numbered data frames of stored data for swapping into a memory. Each frame contains storage blocks of space. A memory is connected to the storage device and comprises a cache comprising numbered pages for storing swapped frames and a page list heads list comprising at least one list head entry. Each numbered page contains data frames that contain memory blocks for data storage or header frames that contain frame meta data. Each such list head entry stores a page number identifying a first of the numbered pages that contains free memory blocks of a given block size. A processor is connected to the memory and comprises means for allocating the one memory block responsive to a memory request by looking up the numbered page identified by the page number stored in the one list head entry.