Abstract: A method and apparatus for generating logical frames from arbitrating among packets is disclosed. An integrated circuit (IC) includes an arbitration circuit configured to generate a logical frame having a first number of bytes by selecting at least one a plurality of packets received from different functional circuit blocks. At least one of the plurality of packets is of a different data size than at least one other one of the plurality of packets. The arbitration circuit is configured to, when selecting two or more of the plurality of packets, generate the logical frame by concatenating selected packets together. The IC further includes a framing circuit configured to generate, based on the logical frame, a physical frame for an outgoing transmission over a serial communications link, wherein the physical frame comprises a second number of bytes that is less than or equal to the first number of bytes.

Abstract: A method and apparatus for logical-physical frame conversion in a serial link application is disclosed. An integrated circuit (IC) includes a serializer-deserializer (SERDES) coupled to a communications link and configured to convert outgoing data transmissions from parallel to serial and convert incoming data transmissions from serial to parallel. A framing unit is coupled to the SERDES and configured to convert data between a logical frame format for parallel transfer and a physical frame format for serial transfer over the communications link. The logical frame has a first number of bytes and the physical frame has a second number of bytes less than or equal to the first number. The first number is variable and the second number is fixed. The framing unit is further configured to convert data between the logical frame format and the physical frame format when the first number is a non-integral power of two.

Abstract: A method and apparatus for generating logical frames from arbitrating among packets is disclosed. An integrated circuit (IC) includes an arbitration circuit configured to generate a logical frame having a first number of bytes by selecting at least one a plurality of packets received from different functional circuit blocks. At least one of the plurality of packets is of a different data size than at least one other one of the plurality of packets. The arbitration circuit is configured to, when selecting two or more of the plurality of packets, generate the logical frame by concatenating selected packets together. The IC further includes a framing circuit configured to generate, based on the logical frame, a physical frame for an outgoing transmission over a serial communications link, wherein the physical frame comprises a second number of bytes that is less than or equal to the first number of bytes.

Abstract: A method and apparatus for logical-physical frame conversion in a serial link application is disclosed. An integrated circuit (IC) includes a serializer-deserializer (SERDES) coupled to a communications link and configured to convert outgoing data transmissions from parallel to serial and convert incoming data transmissions from serial to parallel. A framing unit is coupled to the SERDES and configured to convert data between a logical frame format for parallel transfer and a physical frame format for serial transfer over the communications link. The logical frame has a first number of bytes and the physical frame has a second number of bytes less than or equal to the first number. The first number is variable and the second number is fixed. The framing unit is further configured to convert data between the logical frame format and the physical frame format when the first number is a non-integral power of two.

Abstract: A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Abstract: A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: The present invention is a method and apparatus for synchronizing source I/O without synchronizers using temporal delay queues. A TDQ is used to store the incoming data in phase with a local clock instead of synchronizers. The latency for the entire system is defaulted to the maximum value supported by the system, which ensures that erroneous data is not written after error-free data is read. In one embodiment, run mode data still in transit is preserved when the switch is made by the IOB from run to control mode. Since a pull model is used, valid data is always presented on the IOB interface during run mode. Since the system is source synchronous, the receive data is written into a register using the Send clk instead of the local clock.

Abstract: According to the invention, a matrix of elements is processed in a processor. A first subset of matrix elements is loaded from a first location and a second subset of matrix elements is loaded from a second location. A third subset of matrix elements is stored in a first destination and a fourth subset of matrix elements is stored in a second destination. The loading and storing steps result from the same instruction issue.

Abstract: An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

Abstract: An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.