Patents by Inventor Michael W. Rodehamel

Michael W. Rodehamel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
    Patent number: 5903908
    Abstract: A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: May 11, 1999
    Assignee: Intel Corporation
    Inventors: Gurbir Singh, Konrad K. Lai, Michael W. Rodehamel