Abstract: An interrupt request router is described. The interrupt request router stores a configuration value in a register, receives an interrupt request signal of a first plurality of interrupt request signals, and generates an interrupt request signal of a second plurality of interrupt request signals. The interrupt request signal of a second plurality of interrupt request signals is determined by the configuration value.

Abstract: A binary add signal selection type wherein carry signals rather than the usual sum signals are selected from presumed signals by multiplex switching in each bit slice cell of the adder. The new adder is organized into propagation delay time determined stages which include a plurality of sub-stages of multiple bit slice cells each with the carry signals from a previous stage performing the multiplex carry-selection in each stage. The resulting adder is of regular circuit form and adapted to modern fabrication techniques including VLSI and standard cell. arrangements. Mathematical and graphic comparison of the new adder with plural existing adder architectures are included.

Abstract: A binary adder of the carry multiplex signal selection type wherein multiple levels of multiplexing between parallel carry paths is used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria. The resulting adder employs a plurality of different adder stages of successively increasing complexity and achieves performance time that can be characterized as being of the order of Log.sub.2 (n), wherein n represents bit count, and as requiring a gate count that is of the order of n. Both internal arrangement of the adder stages and interconnection arrangements therefor are disclosed.