Patents by Inventor Michael W. Sheperek

Michael W. Sheperek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11520487
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael W. Sheperek, James P. Crowley
  • Patent number: 10872008
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a first physical address corresponding to a logical address and data and initiating storage of the data at the first physical address. The memory controller sends a message indicating that the data has been successfully stored at the first physical address before determining if the data was successfully stored at the first physical address. Upon determining that the data failed to store at the first physical address, the memory controller retrieves the data from a volatile memory associated with the first physical address. The memory controller sends a request and receives a second physical address for the retrieved data. The memory controller initiates storage of the data at the second physical address.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 22, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: James P. Crowley, Michael W. Sheperek
  • Publication number: 20200117373
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 16, 2020
    Inventors: Michael W. Sheperek, James P. Crowley
  • Patent number: 10534551
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 14, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael W. Sheperek, James P. Crowley
  • Publication number: 20190391867
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a first physical address corresponding to a logical address and data and initiating storage of the data at the first physical address. The memory controller sends a message indicating that the data has been successfully stored at the first physical address before determining if the data was successfully stored at the first physical address. Upon determining that the data failed to store at the first physical address, the memory controller retrieves the data from a volatile memory associated with the first physical address. The memory controller sends a request and receives a second physical address for the retrieved data. The memory controller initiates storage of the data at the second physical address.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: James P. Crowley, Michael W. Sheperek
  • Publication number: 20190391747
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Michael W. Sheperek, James P. Crowley
  • Patent number: 9257145
    Abstract: A disk drive is disclosed comprising a disk comprising a track, wherein the track comprises a sync mark. The disk drive further comprises a head comprising a plurality of read sensors including a first read sensor, and a second read sensor separated from the first read sensor by a down-track spacing. A first time-stamp (TS1) is generated after detecting the sync mark using the first read sensor as the disk rotates, and a second time-stamp (TS2) is generated after detecting the sync mark using the second read sensor as the disk rotates. A calibration value representing the down-track spacing is generated based on the TS1 and the TS2.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 9, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Paul E. Soderbloom, Davide Giovenzana, Michael W. Sheperek
  • Patent number: 7097110
    Abstract: Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Michael W. Sheperek, Bryan E. Bloodworth