Abstract: The present innovation is directed to a single-chip integrated circuit power amplifier configured to employ the efficiency enhancement techniques utilized in Doherty amplifiers. The single-chip integrated circuit power amplifier may be implemented using uniquely designed biasing circuits as described herein. Also, the use of combined HBT/FET processes and a lumped quarter-wavelength transformer may be inherently well suited for the implementation of Doherty amplifiers in the single-chip techniques described herein.

Abstract: A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.

Abstract: A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.

Abstract: The present innovation is directed to a single-chip integrated circuit power amplifier configured to employ the efficiency enhancement techniques utilized in Doherty amplifiers. The single-chip integrated circuit power amplifier may be implemented using uniquely designed biasing circuits as described herein. Also, the use of combined HBT/FET processes and a lumped quarter-wavelength transformer may be inherently well suited for the implementation of Doherty amplifiers in the single-chip techniques described herein.

Abstract: A calibration procedure for vector network analyzers utilizing a known standard, an unknown standard and a pair of offsets bearing a known length ratio (2:1) between them whereby measurements taken on the standards and their combinations with the offsets result in self-verifying redundant equations which furnish: (1) error terms according to well-known flow graph models, (2) the reflection of the unknown standard, (3) the transmission factor of the waveguiding medium from which the offsets are realized regardless of the waveguide's loss or dispersion, and (4) a figure of merit (corruption coefficient) for the quality of the acquired raw data without the necessity for computing the error terms, connecting verification standards or otherwise completing the calibration process.