Patents by Inventor Michael W. Williams
Michael W. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240068408Abstract: A system includes an injector having a scheduling valve assembly and a nozzle in fluid communication with the valve assembly. The scheduling valve assembly is configured for regulation of flow from an inlet of the injector to the nozzle. The injector includes two fluid circuits between the inlet of the injector and two respective outlets of the nozzle for staged flow output from the nozzle. A first one of the two fluid circuits is a primary circuit, and a second one of the two fluid circuits is a secondary circuit. A solenoid valve is connected in fluid communication with the scheduling valve assembly, wherein the solenoid valve is configured to adjust position of a hydromechanical valve spool of the valve assembly.Type: ApplicationFiled: July 21, 2023Publication date: February 29, 2024Applicant: Collins Engine Nozzles, Inc.Inventors: Brandon P. Williams, Michael Ferrarotti, Murtuza Lokhandwalla, Todd Haugsjaahabink, Russell P. Rourke, Jr., Jay W. Kokas, Richard E. Versailles
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Publication number: 20240068409Abstract: A system includes an injector including a scheduling valve assembly and a nozzle in fluid communication with the valve assembly. The scheduling valve assembly is configured for regulation of flow from an inlet of the injector to the nozzle. The injector includes one fluid circuit between the inlet of the injector and a respective outlet of the nozzle. A solenoid valve is connected in fluid communication with the scheduling valve assembly. The solenoid valve is configured to adjust position of a hydromechanical valve spool of the valve assembly.Type: ApplicationFiled: July 21, 2023Publication date: February 29, 2024Applicant: Collins Engine Nozzles, Inc.Inventors: Brandon P. Williams, Michael Ferrarotti, Murtuza Lokhandwalla, Todd Haugsjaahabink, Russell P. Rourke, JR., Jay W. Kokas, Richard E. Versailles
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Publication number: 20240068664Abstract: A fuel injector for a turbine engine includes a fuel scheduling valve configured for regulation of fuel flow from a fuel inlet, in response to fuel pressure received at the fuel inlet. Primary, secondary and auxiliary fuel circuits receive fuel from the scheduling valve, and an electrically-controlled valve is provided in fluid communication with the auxiliary circuit, which electrically-controlled valve is adapted and configured to actively control fuel through the auxiliary circuit in response to a control signal.Type: ApplicationFiled: July 21, 2023Publication date: February 29, 2024Applicant: Collins Engine Nozzles, Inc.Inventors: Brandon P. Williams, Michael Ferrarotti, Murtuza Lokhandwalla, Todd Haugsjaahabink, Russell P. Rourke, JR., Jay W. Kokas, Richard E. Versailles
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Publication number: 20240068413Abstract: A fuel injector for a turbine engine includes a fuel scheduling valve configured for regulation of fuel flow from a fuel inlet, in response to fuel pressure received at the fuel inlet. Primary, secondary and auxiliary fuel circuits receive fuel from the scheduling valve, and an electrically-controlled valve is provided in fluid communication with the auxiliary circuit, which electrically-controlled valve is adapted and configured to actively control fuel through the auxiliary circuit in response to a control signal. The auxiliary fuel circuit joins with the secondary fuel circuit for delivery to a fuel nozzle.Type: ApplicationFiled: July 21, 2023Publication date: February 29, 2024Applicant: Collins Engine Nozzles, Inc.Inventors: Brandon P. Williams, Michael Ferrarotti, Murtuza Lokhandwalla, Todd Haugsjaahabink, Russell P. Rourke, Jr., Jay W. Kokas, Richard E. Versailles
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Publication number: 20240068407Abstract: A fuel injector for a turbine engine includes a fuel scheduling valve configured for regulation of fuel flow from a fuel inlet in response to fuel pressure received at the fuel inlet. Primary and secondary fuel circuits receive fuel from the scheduling valve, and an electrically-controlled valve is provided in fluid communication with the primary circuit, adapted and configured to actively control fuel through the primary circuit in response to a control signal.Type: ApplicationFiled: July 21, 2023Publication date: February 29, 2024Applicant: Collins Engine Nozzles, Inc.Inventors: Brandon P. Williams, Murtuza Lokhandwalla, Michael Ferrarotti, Todd Haugsjaahabink, Russell P. Rourke, JR., Jay W. Kokas, Richard E. Versailles, Jason A. Ryon, Charles E. Reuter
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Patent number: 9910771Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.Type: GrantFiled: January 2, 2017Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Eng Hun Ooi, Robert J. Royer, Jr., Michael W. Williams, Jeffrey R. Wilcox, Ritesh B. Trivedi, Blaise Fanning
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Publication number: 20170212832Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.Type: ApplicationFiled: January 2, 2017Publication date: July 27, 2017Inventors: Eng Hun Ooi, Robert J. Royer, Michael W. Williams, Jeffrey R. Wilcox, Ritesh B. Trivedi, Blaise Fanning
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Patent number: 9535829Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.Type: GrantFiled: July 26, 2013Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Eng Hun Ooi, Robert J. Royer, Jr., Michael W. Williams, Jeffrey R. Wilcox, Ritesh B. Trivedi, Blaise Fanning
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Patent number: 9036718Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.Type: GrantFiled: December 18, 2013Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: David J. Zimmerman, Michael W. Williams
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Publication number: 20150032941Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.Type: ApplicationFiled: July 25, 2013Publication date: January 29, 2015Inventors: Eng Hun Ooi, Robert J. Royer, JR., Michael W. Williams, Jeffrey R. Wilcox, Ritesh B. Trivedi, Blaise Fanning
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Publication number: 20140108696Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Inventors: David J. Zimmerman, Michael W. Williams
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Patent number: 8619883Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.Type: GrantFiled: August 24, 2009Date of Patent: December 31, 2013Assignee: Intel CorporationInventors: David J. Zimmerman, Michael W. Williams
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Patent number: 8161356Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.Type: GrantFiled: March 28, 2008Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: Kuljit S. Bains, John Halbert, Michael W. Williams
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Publication number: 20090316800Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.Type: ApplicationFiled: August 24, 2009Publication date: December 24, 2009Applicant: Intel CorporationInventors: David J. Zimmerman, Michael W. Williams
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Publication number: 20090249169Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: KULJIT S. BAINS, John Halbert, Michael W. Williams
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Patent number: 7580465Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.Type: GrantFiled: June 30, 2005Date of Patent: August 25, 2009Assignee: Intel CorporationInventors: David J. Zimmerman, Michael W. Williams
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Patent number: 7445132Abstract: A gas cartridge actuation state determination system includes a puncture pin adapted to abut an end of the gas cartridge. A load sensor coupled to and in line with the puncture pin. A spring bears against the load sensor. The spring's force is such that it is insufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has not been punctured, but is sufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has already been punctured. In addition, the spring's force is such that it will be approximately zero after the puncture pin has been driven through the end that has already been punctured. A device coupled to the load sensor determines when the spring force is approximately zero.Type: GrantFiled: August 24, 2005Date of Patent: November 4, 2008Assignee: The United States of America as represented by the Secretary of the NavyInventor: Michael W. Williams
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Publication number: 20080151591Abstract: In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes in the memory chips are to be used to carry read data in response to a read request and whether some of the interface lanes are used for carrying read data signals or command signals. Other embodiments are described.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Kevin J. Doran, Joseph H. Salmon, Michael W. Williams
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Patent number: 7353329Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.Type: GrantFiled: September 29, 2003Date of Patent: April 1, 2008Assignee: Intel CorporationInventors: Robert M. Ellis, Kuljit S. Bains, Chris B. Freeman, John B. Halbert, Narendra S. Khandekar, Michael W. Williams
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Patent number: D1019672Type: GrantFiled: July 28, 2021Date of Patent: March 26, 2024Assignee: HACH COMPANYInventors: Michael Jonathan Tschampl, Reece W. Hopkins, Jennifer Kotch, Heather Nicole Goodrich, Victor Ray Williams