Abstract: Described herein are various coupling systems to be used with storage units that are selectively coupled and decoupled. The coupling systems may be used with storage units that are stackable and/or transportable, thus allowing the storage units to function well within a large stationary environment, such as a basement, and also for a subset of the storage units to be selected and easily moved to another location.

Abstract: A fuel injector for a turbine engine includes a fuel scheduling valve configured for regulation of fuel flow from a fuel inlet in response to fuel pressure received at the fuel inlet. Primary and secondary fuel circuits receive fuel from the scheduling valve, and an electrically-controlled valve is provided in fluid communication with the primary circuit, adapted and configured to actively control fuel through the primary circuit in response to a control signal.

Abstract: A downhole tool for use in a downhole drill string is provided. The downhole tool includes a rotor movably coupled within a stator, and a drive shaft movably coupled within a bearing housing. The drive shaft has a first end coupled with the rotor and a second end coupled with a drill bit. Bearing assemblies interfaces engagement between the drive shaft and the bearing housing, including polycrystalline diamond elements, each with an engagement surface, and an opposing engagement surface of a non-superhard metal.

Abstract: A fuel injector for a turbine engine includes a fuel scheduling valve configured for regulation of fuel flow from a fuel inlet, in response to fuel pressure received at the fuel inlet. Primary, secondary and auxiliary fuel circuits receive fuel from the scheduling valve, and an electrically-controlled valve is provided in fluid communication with the auxiliary circuit, which electrically-controlled valve is adapted and configured to actively control fuel through the auxiliary circuit in response to a control signal.

Abstract: Disclosed herein are methods for the production of Cannabis meristem explants from dry seeds. Also described are methods of transforming and gene editing using the Cannabis meristem explants disclosed herein.

Abstract: A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: A gas cartridge actuation state determination system includes a puncture pin adapted to abut an end of the gas cartridge. A load sensor coupled to and in line with the puncture pin. A spring bears against the load sensor. The spring's force is such that it is insufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has not been punctured, but is sufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has already been punctured. In addition, the spring's force is such that it will be approximately zero after the puncture pin has been driven through the end that has already been punctured. A device coupled to the load sensor determines when the spring force is approximately zero.

Abstract: In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes in the memory chips are to be used to carry read data in response to a read request and whether some of the interface lanes are used for carrying read data signals or command signals. Other embodiments are described.

Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.