Patents by Inventor Michael W. Yung
Michael W. Yung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9721332Abstract: A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.Type: GrantFiled: February 12, 2016Date of Patent: August 1, 2017Assignee: HRL Laboratories, LLCInventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
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Publication number: 20160239947Abstract: A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.Type: ApplicationFiled: February 12, 2016Publication date: August 18, 2016Inventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
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Patent number: 9407239Abstract: An automatic tuning circuit for matching an antenna to a radio receiver. The automatic tuning circuit includes a tunable non-Foster circuit for coupling the receiver and the antenna; and sensing and feedback circuits for sensing the combined capacitance of the tunable non-Foster circuit and the antenna and for tuning the tunable non-Foster circuit to automatically minimize the combined capacitance of the tunable non-Foster circuit and the antenna.Type: GrantFiled: May 15, 2012Date of Patent: August 2, 2016Assignee: HRL Laboratories, LLCInventors: Carson R. White, Joseph S. Colburn, Michael W. Yung, Donald A. Hitko
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Patent number: 9054798Abstract: A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.Type: GrantFiled: July 5, 2012Date of Patent: June 9, 2015Assignee: HRL Laboratories, LLCInventors: Zhiwei Xu, Michael W. Yung, Donald A. Hitko, Carson R. White
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Patent number: 8996431Abstract: A spike domain asynchronous neuron circuit includes a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output, a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output, a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit, and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.Type: GrantFiled: November 16, 2012Date of Patent: March 31, 2015Assignee: HRL Laboratories, LLCInventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
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Patent number: 8988173Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).Type: GrantFiled: April 6, 2012Date of Patent: March 24, 2015Assignee: HRL Laboratories, LLCInventors: Donald A. Hitko, Carson R. White, Michael W. Yung, David S. Matthews, Susan L. Morton, Jason W. May, Joseph S. Colburn
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Patent number: 8975935Abstract: A delay circuit includes a first flip flop (FF), a transistor connected to the FF, a first resistor capacitor circuit (RCC) coupled to the transistor and between a voltage and a ground, a first comparator for comparing an output of the first RCC and a voltage reference, gate logic coupled to the input line and to an output of the first FF and to a second FF, a second transistor coupled to the second FF, a second RCC coupled to the second transistor and between the voltage and ground, a second comparator for comparing an output of the second RCC and the voltage reference and coupled to the first FF, and output logic coupled to the first and second comparators.Type: GrantFiled: June 28, 2013Date of Patent: March 10, 2015Assignee: HRL Laboratories, LLCInventors: Michael W. Yung, Jose M. Cruz-Albrecht
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Publication number: 20140032460Abstract: A spike domain asynchronous neuron circuit includes a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output, a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output, a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit, and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.Type: ApplicationFiled: November 16, 2012Publication date: January 30, 2014Applicant: HRL LABRORATORIES, LLCInventors: Jose Cruz-Albrecht, Michael W. Yung, Narayan Srinivasa
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Patent number: 8374561Abstract: A non-Foster impedance power amplifier has a current amplifying device coupled in either an emitter-follower or source-follower configuration with a reactive load such as an antenna load. A negative impedance circuit is provided upstream of a gate or base or other control element of said current amplifying device.Type: GrantFiled: April 27, 2010Date of Patent: February 12, 2013Assignee: HRL Laboratories, LLCInventors: Michael W. Yung, Donald A. Hitko
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Publication number: 20130009722Abstract: An automatic tuning circuit for matching an antenna to a radio receiver. The automatic tuning circuit includes a tunable non-Foster circuit for coupling the receiver and the antenna; and sensing and feedback circuits for sensing the combined capacitance of the tunable non-Foster circuit and the antenna and for tuning the tunable non-Foster circuit to automatically minimize the combined capacitance of the tunable non-Foster circuit and the antenna.Type: ApplicationFiled: May 15, 2012Publication date: January 10, 2013Applicant: HRL LABORATORIES, LLCInventors: Carson R. White, Joseph S. Colburn, Michael W. Yung, Donald A. Hitko
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Publication number: 20130009720Abstract: An automatic tuning circuit for matching an antenna to a radio receiver. The automatic tuning circuit includes a tunable non-Foster circuit for coupling the receiver and the antenna; and sensing and feedback circuits for sensing the combined capacitance of the tunable non-Foster circuit and the antenna and for tuning the tunable non-Foster circuit to automatically minimize the combined capacitance of the tunable non-Foster circuit and the antenna.Type: ApplicationFiled: July 6, 2011Publication date: January 10, 2013Applicant: HRL LABORATORIES, LLCInventors: Carson R. White, Joseph S. Colburn, Michael W. Yung, Donald A. Hitko
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Publication number: 20130009724Abstract: A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.Type: ApplicationFiled: July 5, 2012Publication date: January 10, 2013Applicant: HRL Laboratories, LLCInventors: Zhiwei Xu, Michael W. Yung, Donald A. Hitko, Carson R. White
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Publication number: 20120256709Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).Type: ApplicationFiled: April 6, 2012Publication date: October 11, 2012Applicant: HRL LABORATORIES, LLCInventors: Donald A. Hitko, Carson R. White, Michael W. Yung, David S. Matthews, Susan L. Morton, Jason W. May, Joseph S. Colburn
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Patent number: 5744284Abstract: A method for fabricating resilient z-axis contacts to electrically interconnect IC wafers or MCMs in 3-D integrated circuits uses photolithography to provide larger carrier sizes, higher contact densities by decreasing the spacing, smaller contact footpads, and precise control of the contact's shape and position. The contacts are fabricated by forming photoresist patterns on the carrier's top and bottom surfaces that are initially rectangular, and then reflowing the photoresist materials to provide smooth surfaces suitable for forming the metal contacts, and depositing metal layers over the respective patterns. Second photoresist patterns are formed over respective metal layers to conform with the contact's shape, the metal is etched away according to the pattern, and the photoresists are removed such that the remaining metalization forms a resilient z-axis contact that is attached to the carrier and extends therefrom with a predetermined shape.Type: GrantFiled: April 9, 1997Date of Patent: April 28, 1998Assignee: Hughes Aircraft CompanyInventors: Soyeon P. Laub, Michael J. Little, James A. Foschaar, Hugh L. Garvin, Michael W. Yung
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Patent number: 5371744Abstract: A system (30) and method is provided for enumerating acyclic paths in an information processing system. The system (30) incorporates multiple processor nodes (18) or functional units interconnected by point-to-point links (20). The hardware of the information processor is represented as a mixed graph with graph nodes (32) for processors and with graph edges (34) representing communication links (20). All the useful paths from the source nodes of the data to the destination nodes of the data are determined in accordance with the system and method of the present invention. These paths are then stored as a list in a table indexed by the source and destination nodes. Thus, when the need for a interprocessor communication path arises, the table can be consulted to find a permissible path. The system (30) efficiently performs interprocessor communication routing and can be utilized in real time.Type: GrantFiled: March 23, 1992Date of Patent: December 6, 1994Assignee: Hughes Aircraft CompanyInventors: Michael L. Campbell, Michael W. Yung
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Patent number: 5274264Abstract: Short circuits in the power distribution network of a circuit structure are accurately located and isolated by providing selected power distribution lines with areas whose width is reduced sufficiently to produce a highly resolved current-induced hot spot in response to a downstream short circuit. The invention is particularly applicable to crossovers of power distribution lines separated by an insulating layer. The upper line is divided into a plurality of spaced parallel channels in the crossover vicinity. The channels each include areas of further reduced width at their opposite ends, preferably outside of but proximate to the crossover area, where the hot spots are formed. A short circuit on any of the channels is isolated by cutting at the areas of further reduced width on either side of the fault.Type: GrantFiled: December 12, 1990Date of Patent: December 28, 1993Assignee: Hughes Aircraft CompanyInventor: Michael W. Yung
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Patent number: 4970724Abstract: An array of processing element nodes are provided on a semiconductor wafer. A mixed redundancy approach is preferably employed wherein two spare core logic circuit modules 52, 58 are available for use at each node. Each spare core logic module can be connected to one of four different nodes. An H-net 94 interconnects adjacent nodes in such manner that faults in the circuit modules can be easily tested and repaired.Type: GrantFiled: December 22, 1988Date of Patent: November 13, 1990Assignee: Hughes Aircraft CompanyInventor: Michael W. Yung
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Patent number: 4908525Abstract: To provide for improving the yield in the manufacture of wafer-scale integrated (WSI) or restructurable very-large-scale integrated (RVLSI) CMOS circuitry, a low power switch circuit, fabricated with standard CMOS process, provides both discretionary disconnect and connect capability, by a simple cut of one metal line to replace defective components with redundant good ones. The circuit uses either a reverse bias p-n junction or a transistor biased for sub-threshold conduction as a "pull-up" device, hence consuming very little power in either the original or the "cut" state. Large numbers of this switch can be incorporated into complex circuits without significantly loading the power supply.Type: GrantFiled: February 3, 1989Date of Patent: March 13, 1990Assignee: The United States of America as represented by the Secretary of the Air ForceInventor: Michael W. Yung