Abstract: Aspects of this disclosure implement a power recovery method without user intervention to drain all power rails of a non-booting information handling system and restoring power after a full drain sequence has been completed. A method may include determining, by a management circuit, a failure occurs preventing handoff from a basic input/output system (BIOS) to an operating system; based on determining the failure occurs: disconnecting, by the management circuit of the information handling system, one or more active power sources and one or more real-time clock (RTC) power sources; and after a predetermined delay following disconnecting: re-connecting, by the management circuit of the information handling system, the at least one of the one or more active power sources or the one or more real-time clock (RTC) power sources; and booting the information handling system. Other aspects are also disclosed.

Abstract: Aspects of this disclosure implement a power recovery method without user intervention to drain all power rails of a non-booting information handling system and restoring power after a full drain sequence has been completed. A method may include determining, by a management circuit, a failure occurs preventing handoff from a basic input/output system (BIOS) to an operating system; based on determining the failure occurs: disconnecting, by the management circuit of the information handling system, one or more active power sources and one or more real-time clock (RTC) power sources; and after a predetermined delay following disconnecting: re-connecting, by the management circuit of the information handling system, the at least one of the one or more active power sources or the one or more real-time clock (RTC) power sources; and booting the information handling system. Other aspects are also disclosed.

Abstract: Systems and methods for memory serviceability mitigation are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: after failure of a memory device, notify a cloud service and enter a mitigation mode of operation with respect to the memory device, receive a message from the cloud service indicative of the provisioning of a replacement memory device, and, in response to the message and upon detection of a chassis intrusion event, leave the mitigation mode of operation with respect to the replacement memory device.

Abstract: Systems and methods for memory serviceability mitigation are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: after failure of a memory device, notify a cloud service and enter a mitigation mode of operation with respect to the memory device, receive a message from the cloud service indicative of the provisioning of a replacement memory device, and, in response to the message and upon detection of a chassis intrusion event, leave the mitigation mode of operation with respect to the replacement memory device.

Abstract: A system for secure processing of intra-processor data comprising firmware configured to operate on a processor. An operating system configured to operate on the processor. Payload configured to operate on the processor. An embedded controller coupled to the firmware, the operating system and the payload, wherein the embedded controller is configured to enable messaging between the firmware, the operating system and the payload.

Abstract: A system for secure processing of intra-processor data comprising firmware configured to operate on a processor. An operating system configured to operate on the processor. Payload configured to operate on the processor. An embedded controller coupled to the firmware, the operating system and the payload, wherein the embedded controller is configured to enable messaging between the firmware, the operating system and the payload.

Abstract: Disclosed herein are methods, systems, and processes to embed forensic and triage data in memory dumps. Memory dump data being written to kernel memory of a computing system by a firmware interface is detected. An operating mode of an operating system executing on the computing system is activated. Hardware forensic data is generated by reading local computer bus data, firmware event log data, and memory mapped input/output (I/O) data associated with the computing system. The hardware forensic data is then stored in a memory location of the kernel memory, causing the hardware forensic data to be included in the memory dump data being written to kernel memory.

Abstract: Disclosed herein are methods, systems, and processes to embed forensic and triage data in memory dumps. Memory dump data being written to kernel memory of a computing system by a firmware interface is detected. An operating mode of an operating system executing on the computing system is activated. Hardware forensic data is generated by reading local computer bus data, firmware event log data, and memory mapped input/output (I/O) data associated with the computing system. The hardware forensic data is then stored in a memory location of the kernel memory, causing the hardware forensic data to be included in the memory dump data being written to kernel memory.