Patents by Inventor Michael Wedlake
Michael Wedlake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10343253Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.Type: GrantFiled: June 23, 2014Date of Patent: July 9, 2019Assignee: GLOBALFOUNDRIES, INC.Inventors: Abner Bello, Michael Wedlake
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Patent number: 9412740Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.Type: GrantFiled: September 16, 2015Date of Patent: August 9, 2016Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Ruilong Xie, Michael Wedlake, Xiuyu Cai, Ali Khakifirooz, Kangguo Cheng
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FINFET DEVICE WITH A SUBSTANTIALLY SELF-ALIGNED ISOLATION REGION POSITIONED UNDER THE CHANNEL REGION
Publication number: 20160190306Abstract: One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone -
Patent number: 9318388Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.Type: GrantFiled: May 29, 2015Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone
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Publication number: 20160005733Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Ruilong Xie, Michael Wedlake, Xiuyu Cai, Ali Khakifirooz, Kangguo Cheng
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Publication number: 20150371912Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.Type: ApplicationFiled: June 23, 2014Publication date: December 24, 2015Inventors: Abner Bello, Michael Wedlake
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Patent number: 9165836Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.Type: GrantFiled: April 1, 2014Date of Patent: October 20, 2015Assignees: GLOBALFOUNDRIES INC., International Business Machines CorporationInventors: Ruilong Xie, Michael Wedlake, Xiuyu Cai, Ali Khakifirooz, Kangguo Cheng
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Publication number: 20150294912Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.Type: ApplicationFiled: May 29, 2015Publication date: October 15, 2015Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone
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Publication number: 20150279742Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.Type: ApplicationFiled: April 1, 2014Publication date: October 1, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Michael Wedlake, Xiuyu Cai, Ali Khakifirooz, Kangguo Cheng
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Publication number: 20150228511Abstract: Methods and a system for processing semiconductor substrates are provided. A method of processing a semiconductor substrate includes selecting a predetermined vibration profile that will achieve predetermined material removal characteristics from the semiconductor substrate in a chemical mechanical planarization (CMP) polish, actuating a vibration actuator based on the predetermined vibration profile, and polishing the semiconductor substrate based substantially entirely on the predetermined vibration profile achieved by actuation of the vibration actuator.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: Globalfoundries, Inc.Inventor: Michael Wedlake
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Patent number: 9093302Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.Type: GrantFiled: November 13, 2013Date of Patent: July 28, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone
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Publication number: 20150129934Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone
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Patent number: 8232209Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.Type: GrantFiled: February 11, 2011Date of Patent: July 31, 2012Assignee: Spansion LLCInventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
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Publication number: 20110136268Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.Type: ApplicationFiled: February 11, 2011Publication date: June 9, 2011Applicant: SPANSION LLCInventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
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Patent number: 7915169Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.Type: GrantFiled: November 2, 2007Date of Patent: March 29, 2011Assignee: Spansion LLCInventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert
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Publication number: 20090117734Abstract: A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.Type: ApplicationFiled: November 2, 2007Publication date: May 7, 2009Applicant: SPANSION LLCInventors: Christopher E. Brannon, Michael Wedlake, Chris A. Nauert