Patents by Inventor Michael Wentling

Michael Wentling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual sided integrated circuit chip package with offset wire bonds and support block cavities
    Patent number: 5545922
    Abstract: A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: August 13, 1996
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima, Keiichi Tsujimoto, Nobuaki Sato
  • Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
    Patent number: 5527740
    Abstract: A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: June 18, 1996
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima, Keiichi Tsujimoto, Nobuaki Sato
  • Method for constructing a dual sided, wire bonded integrated circuit chip package
    Patent number: 5366933
    Abstract: A method for constructing a dual sided integrated circuit chip package. A leadframe is formed comprising a set of die pads, and a set of lead fingers corresponding to each die pad. An integrated circuit die is disposed onto a first side and a second side of each die pad. Each integrated circuit die is wire bonded to the corresponding lead fingers. The temperature during the second side die attach and wire bonding steps is controlled and/or compatible materials are selected to prevent warping of the leadframe, and special steps are also implemented to eliminate mold flash, plastic mold cracking and overcuring and increasing the adhesion.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: November 22, 1994
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima