Abstract: A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.

Abstract: A method, system, and product are disclosed for determining an inductance of an entire integrated circuit package taken as a whole. A model is generated of the entire integrated circuit package which has a first port, a second port, and a third port. The first port of the model is coupled in parallel to an energy source and a resistor having a known resistance. The second port of the model is shorted. And, the third port of the model is opened. The package is simulated by exciting the first port utilizing the energy source and measuring a voltage at the first port in order to produce a waveform. A time constant is determined utilizing the waveform. The inductance of the entire integrated circuit package is then determined from the first port with respect to the second port using the known resistance and the time constant.