Abstract: Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converter circuits may be synchronized, such that, for example, sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits. A common phase reference corresponding to an AC voltage phase for the AC load bus may be provided, and the PWM cycles of each of the power converter circuits may synchronized, e.g., phase locked, to the common phase reference. More particularly, the respective PWM cycles of the UPSs may be phase locked to phase locked sinusoidal reference signals generated at each of the UPSs. Sampling for other control functions may also be synchronized to the PWM cycles.

Abstract: Status of a bypass source of parallel-connected UPSs is determined from a load share when a loading of the parallel-connected UPSs meets a predetermined criterion. Status of a bypass source of the parallel-connected UPSs is determined from a bypass source voltage when the loading of the parallel-connected UPSs fails to meet the predetermined criterion. The loading may include an aggregate loading, and failure of a bypass source of a UPS may be identified responsive to detecting that a load share of the UPS is less than a predetermined proportion of the aggregate loading. Alternatively, failure of the bypass source may be identified by detecting that a bypass voltage fails to meet a predetermined criterion. Bypass circuits of the UPSs may be controlled responsive to a load share and/or a bypass source voltage.

Abstract: Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converter circuits may be synchronized, such that, for example, sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits. A common phase reference corresponding to an AC voltage phase for the AC load bus may be provided, and the PWM cycles of each of the power converter circuits may synchronized, e.g., phase locked, to the common phase reference. More particularly, the respective PWM cycles of the UPSs may be phase locked to phase locked sinusoidal reference signals generated at each of the UPSs. Sampling for other control functions may also be synchronized to the PWM cycles.

Abstract: Status of a bypass source of parallel-connected UPSs is determined from a load share when a loading of the parallel-connected UPSs meets a predetermined criterion. Status of a bypass source of the parallel-connected UPSs is determined from a bypass source voltage when the loading of the parallel-connected UPSs fails to meet the predetermined criterion. The loading may include an aggregate loading, and failure of a bypass source of a UPS may be identified responsive to detecting that a load share of the UPS is less than a predetermined proportion of the aggregate loading. Alternatively, failure of the bypass source may be identified by detecting that a bypass voltage fails to meet a predetermined criterion. Bypass circuits of the UPSs may be controlled responsive to a load share and/or a bypass source voltage.