Abstract: A phase-locked loop. The phase-locked loop has a phase ascertaining unit for detecting a phase of a reference signal and outputting a measurement signal, a phase deviation ascertaining unit generating an error signal from the measurement signal and a target signal, a loop filter for filtering the error signal, a modulator unit for modulating the filtered error signal and generating a tune signal, and an oscillator for generating an output signal from the tune signal. A feedback signal formed from an output signal of the phase-locked loop is supplied to the phase ascertaining unit. The phase-locked loop includes: a divider unit configured to generate a modulator clock pulse signal from an oscillator clock pulse signal of the oscillator and to supply the modulator clock pulse signal to the modulator unit, and a sampler unit configured to detect a mismatch between the reference signal and the modulator clock pulse signal.

Abstract: A phase-locked loop. The phase-locked loop includes: a phase ascertaining unit for detecting a phase difference between a reference signal and a feedback signal, and outputting a measurement signal representing the phase difference; a phase deviation ascertaining unit for generating an error signal from the measurement signal and a target signal; a loop filter for filtering the error signal; a modulator unit for modulating the filtered error signal, and generating a tune signal, and an oscillator for generating an output signal from the tune signal. A feedback signal derived from the output signal of the phase-locked loop is supplied to the phase ascertaining unit. The modulator unit has a modulator and a scrambler installed downstream. The modulator unit has an impairment module configured to ascertain a signal impairment from metadata of the scrambler and from predefined calibration data, and is configured to feed signal impairments back to the modulator.

Abstract: A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

Abstract: A method for determining a noise power in a phase-locked loop of a technical system. The method includes: providing at least one resonator in the phase-locked loop; configuring the at least one resonator with respect to a center frequency, a bandwidth, and/or an integration time, wherein the integration time is specific to a time period for which the noise power is determined; determining the noise power in the phase-locked loop by means of the at least one resonator based on a summation of an energy of a phase error of the phase-locked loop for the configured integration time. A computer program, a device, and a storage medium, are also described.