Patents by Inventor Michael Wojtowicz

Michael Wojtowicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048184
    Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 2, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Carol O. Namba, Po-Hsin Liu, Sumiko Poust, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
  • Publication number: 20140264448
    Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Northrop Grumman Systems Corporation
    Inventors: CAROL O. NAMBA, Po-Hsin Lin, Poust Sumiko, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
  • Patent number: 8809137
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 19, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Patent number: 8809907
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 19, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Patent number: 8575657
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20130248879
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20120032185
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Application
    Filed: September 8, 2011
    Publication date: February 9, 2012
    Applicant: Northrop Grumman Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Patent number: 8026132
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: September 27, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Publication number: 20090267115
    Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
  • Patent number: 7608865
    Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 27, 2009
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
  • Publication number: 20080251891
    Abstract: The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Yeong-Chang Chou, Peter S. Nam, Chun H. Lin, Augusto Gutierrez, Jeffrey Ming-Jer Yang, Michael Wojtowicz
  • Publication number: 20080153215
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Application
    Filed: February 5, 2008
    Publication date: June 26, 2008
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Publication number: 20070218611
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Application
    Filed: March 14, 2006
    Publication date: September 20, 2007
    Inventors: Rajinder Sandhu, Michael Barsky, Michael Wojtowicz
  • Patent number: 7041579
    Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: May 9, 2006
    Assignee: Northrop Grumman Corporation
    Inventors: Michael Edward Barsky, Michael Wojtowicz, Rajinder Randy Sandhu
  • Publication number: 20050090076
    Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Michael Barsky, Michael Wojtowicz, Rajinder Sandhu
  • Patent number: 6710379
    Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 23, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
  • Publication number: 20030141519
    Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 31, 2003
    Applicant: TRW Inc.
    Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
  • Patent number: 6528829
    Abstract: The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: March 4, 2003
    Assignee: TRW Inc.
    Inventors: Augusto L. Gutierrez-Aitken, Aaron K. Oki, Michael Wojtowicz, Dwight C. Streit, Thomas R. Block, Frank M. Yamada
  • Patent number: 6515316
    Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 4, 2003
    Assignee: TRW Inc.
    Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
  • Publication number: 20020149033
    Abstract: A heterojunction bipolar transistor (HBT) (20) with alternating layers of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) with varying Al composition forming a graded superlattice structure in the base layer (28) includes. The thin layers of AlGaN in the base layer (28) increases the base p-type carrier concentration. Grading of the Al composition in the thin AlGaN layers induces an electrostatic field across the base layer (28) that increases the carrier velocity and reduces the carrier transit time. The structure thus decreases the transit time and at the same time increases the p-type carrier concentration to improve the operating efficiency of the device.
    Type: Application
    Filed: April 12, 2001
    Publication date: October 17, 2002
    Inventor: Michael Wojtowicz