Patents by Inventor Michael Wojtowicz
Michael Wojtowicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220146816Abstract: An optical assembly including a plurality of metamirrors, where each metamirror includes a substrate, a reflective layer formed to the substrate, an array of optical metaelements extending from the reflective layer and an array of micro-actuators coupled to the substrate opposite to the reflective layer. The combination of the micro-actuators are controlled to control the orientation and bending of the metamirrors to set how the metaelements focus a light beam that is reflected off of the reflective layers.Type: ApplicationFiled: November 11, 2020Publication date: May 12, 2022Inventors: Donald Di Marzio, Stephane Larouche, Vesna Radisic, Michael R. Hachkowski, Jeffrey L. Cavaco, Michael Wojtowicz
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Patent number: 9048184Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.Type: GrantFiled: March 15, 2013Date of Patent: June 2, 2015Assignee: Northrop Grumman Systems CorporationInventors: Carol O. Namba, Po-Hsin Liu, Sumiko Poust, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
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Publication number: 20140264448Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Northrop Grumman Systems CorporationInventors: CAROL O. NAMBA, Po-Hsin Lin, Poust Sumiko, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
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Patent number: 8809137Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: GrantFiled: September 8, 2011Date of Patent: August 19, 2014Assignee: Northrop Grumman Systems CorporationInventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
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Patent number: 8809907Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: GrantFiled: March 14, 2006Date of Patent: August 19, 2014Assignee: Northrop Grumman Systems CorporationInventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
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Patent number: 8575657Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.Type: GrantFiled: March 20, 2012Date of Patent: November 5, 2013Assignee: Northrop Grumman Systems CorporationInventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
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Publication number: 20130248879Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: Northrop Grumman Systems CorporationInventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
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Publication number: 20120032185Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: ApplicationFiled: September 8, 2011Publication date: February 9, 2012Applicant: Northrop Grumman CorporationInventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
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Patent number: 8026132Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: GrantFiled: February 5, 2008Date of Patent: September 27, 2011Assignee: Northrop Grumman Systems CorporationInventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
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Publication number: 20090267115Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Patent number: 7608865Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: GrantFiled: April 28, 2008Date of Patent: October 27, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Publication number: 20080251891Abstract: The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Inventors: Yeong-Chang Chou, Peter S. Nam, Chun H. Lin, Augusto Gutierrez, Jeffrey Ming-Jer Yang, Michael Wojtowicz
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Publication number: 20080153215Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: ApplicationFiled: February 5, 2008Publication date: June 26, 2008Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
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Publication number: 20070218611Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.Type: ApplicationFiled: March 14, 2006Publication date: September 20, 2007Inventors: Rajinder Sandhu, Michael Barsky, Michael Wojtowicz
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Patent number: 7041579Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).Type: GrantFiled: October 22, 2003Date of Patent: May 9, 2006Assignee: Northrop Grumman CorporationInventors: Michael Edward Barsky, Michael Wojtowicz, Rajinder Randy Sandhu
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Publication number: 20050090076Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).Type: ApplicationFiled: October 22, 2003Publication date: April 28, 2005Inventors: Michael Barsky, Michael Wojtowicz, Rajinder Sandhu
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Patent number: 6710379Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: GrantFiled: February 4, 2003Date of Patent: March 23, 2004Assignee: Northrop Grumman CorporationInventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
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Publication number: 20030141519Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: ApplicationFiled: February 4, 2003Publication date: July 31, 2003Applicant: TRW Inc.Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
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Patent number: 6528829Abstract: The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.Type: GrantFiled: March 25, 1999Date of Patent: March 4, 2003Assignee: TRW Inc.Inventors: Augusto L. Gutierrez-Aitken, Aaron K. Oki, Michael Wojtowicz, Dwight C. Streit, Thomas R. Block, Frank M. Yamada
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Patent number: 6515316Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: GrantFiled: July 14, 2000Date of Patent: February 4, 2003Assignee: TRW Inc.Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher