Abstract: Providing predictive instruction dispatch throttling to prevent resource overflow in out-of-order processor (OOP)-based devices is disclosed. In this regard, an OOP-based device includes a system resource that may be consumed or otherwise occupied by instructions, as well as an execution pipeline comprising a decode stage and a dispatch stage. The OOP further maintains a running count and a resource usage threshold. Upon receiving an instruction block, the decode stage extracts a proxy value that indicates an approximate predicted count of instructions within the instruction block that will consume a system resource. The decode stage then increments the running count by the proxy value. The dispatch stage compares the running count to the resource usage threshold before dispatching any younger instruction blocks. If the running count exceeds the resource usage threshold, the dispatch stage blocks dispatching of younger instruction blocks until the running count no longer exceeds the resource usage threshold.

Abstract: Disclosed is a smart, physiology monitoring mouthguard (SPMM) system and method for capturing various physiological data of athletes in real-time for health monitoring. The system is configured to provide real-time and/or recorded physiological data of an athlete to a user, and may be configured to record physiological data of the athlete for later retrieval using sensors and communication systems. Sensors may be chosen based on the anticipated activity or sport, the health and age of the athlete, and size and power requirements of the device. Sensors may include accelerometers, gyroscopes, thermometers, hydrometers, pH, electrolyte (e.g., potassium, sodium, etc.) sensors, and the like. These and other sensors may be configured to measure different physiological data of the athlete, including impact, body temperature, hydration, illness, heart rate, and the like. In some embodiments, sensors on the mouthguard are integrated with external sensors (e.g.

Abstract: Providing efficient handling of branch divergence in vectorizable loops by vector-processor-based devices is disclosed. In some aspects, a vector-processor-based device provides a plurality of processing elements (PEs) coupled to a scheduler circuit comprising a clock cycle threshold and a mask register comprising a plurality of bits corresponding to a plurality of loop iterations of a vectorizable loop to be executed. The scheduler circuit initiates a first execution interval, during which loop iterations of the vectorizable loop are assigned to PEs for parallel execution. If a loop iteration's execution time exceeds the clock cycle threshold, the scheduler circuit sets a mask register bit corresponding to the loop iteration indicating that the loop iteration is incomplete, and defers its execution.

Abstract: A prescription management system is used by an orthodontic or dental lab and a plurality of prescribing users who send prescriptions for customized orthodontic or dental appliances to the lab. The prescriptions are stored in a database selectively accessible by the lab and plurality of prescribing users. A digital workspace is provided in the system in which the lab or prescribing users may create designs for the customized appliances. The designs of the appliances are stored in the database. A tracking record of fabrication of the appliances is stored in the database. A plurality of billings are simultaneously generated in response to the submissions and storage of the prescriptions, the designs of the customized appliances and the fabrication of the designed customized appliances.

Abstract: Providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device provides a vector processor including a plurality of PEs and a decode/control circuit. The decode/control circuit receives an instruction block containing a vectorizable loop comprising a loop body. The decode/control circuit determines how many PEs of the plurality of PEs are required to execute the loop body, and reconfigures the plurality of PEs into one or more fused PEs, each including the determined number of PEs required to execute the loop body. The plurality of PEs, reconfigured into one or more fused PEs, then executes one or more loop iterations of the loop body. Some aspects further include a PE communications link interconnecting the plurality of PEs, to enable communications between PEs of a fused PE and communications of inter-iteration data dependencies between PEs without requiring vector register file access operations.

Abstract: A flexible stretcher having skid plate webbing connected to a surface of the stretcher. The stretcher includes a flexible body with a first surface and a second surface. Skid plate webbing connects to the second surface. In another embodiment, the stretcher has a flexible body with a rectangular shape extending lengthwise in a longitudinal direction. The flexible body has a first surface and a second surface. Structural webbing and skid plate webbing connect to the second surface. The skid plate webbing at least partially overlaps the structural webbing, and where the overlapping occurs, contact points are formed. In another embodiment, a flexible stretcher having a body with a rectangular shape extending lengthwise in a longitudinal direction, a first surface, and a second surface, may be manufactured by attaching structural webbing to the body and attaching skid plate webbing to the second surface of the body.

Abstract: Enabling parallel memory accesses by providing explicit affine instructions in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device implementing a block-based dataflow instruction set architecture (ISA) includes a decoder circuit configured to provide an affine instruction that specifies a base parameter indicating a base value B, a stride parameter indicating a stride interval value S, and a count parameter indicating a count value C. The decoder circuit of the vector-processor-based device decodes the affine instruction, and generates an output stream comprising one or more output values, wherein a count of the output values of the output stream equals the count value C. Using an index X where 0?X<C, each Xth output value in the output stream is generated as a sum of the base value B and a product of the stride interval value S and the index X.

Abstract: Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device includes a vector processor comprising multiple processing elements (PEs) communicatively coupled via a corresponding plurality of channels to a vector register file comprising a plurality of memory banks. The vector processor provides a direct memory access (DMA) controller that is configured to receive a plurality of vectors that each comprise a plurality of vector elements representing operands for processing a loop iteration. The DMA controller arranges the vectors in the vector register file such that, for each group of vectors to be accessed in parallel, vector elements for each vector are stored consecutively, but corresponding vector elements of consecutive vectors are stored in different memory banks of the vector register file.

Abstract: A chute control assembly for a snow thrower having a housing, handle, and a chute includes a control mechanism, a connecting mechanism, and a guide mechanism. The control mechanism includes an actuator mechanism that allows an operator to manually control the orientation of the chute from a position spaced apart from the chute. The connecting mechanism transfers rotation of the actuator mechanism to the guide mechanism. The guide mechanism is attached to the chute and rotates and adjust the orientation of the chute in response to rotation of the actuator mechanism in order to change the direction that snow is thrown from the snow thrower.

Abstract: A chute control assembly for a snow thrower having a housing, handle, and a chute includes a control mechanism, a connecting mechanism, and a guide mechanism. The control mechanism includes an actuator mechanism that allows an operator to manually control the orientation of the chute from a position spaced apart from the chute. The connecting mechanism transfers rotation of the actuator mechanism to the guide mechanism. The guide mechanism is attached to the chute and rotates and adjust the orientation of the chute in response to rotation of the actuator mechanism in order to change the direction that snow is thrown from the snow thrower.

Abstract: A brake carrier casting and a method of making a brake carrier casting. The brake carrier casting may have a first side portion and a second side portion that may be connected by a first bridge and a second bridge. The first side portion, second side portion, first bridge, and second bridge may define an opening of the brake carrier casting.

Abstract: A prescription management system is used by an orthodontic or dental lab and a plurality of prescribing users who send prescriptions for customized orthodontic or dental appliances to the lab. The prescriptions are stored in a database selectively accessible by the lab and plurality of prescribing users. A digital workspace is provided in the system in which the lab or prescribing users may create designs for the customized appliances. The designs of the appliances are stored in the database. A tracking record of fabrication of the appliances is stored in the database. A plurality of billings are simultaneously generated in response to the submissions and storage of the prescriptions, the designs of the customized appliances and the fabrication of the designed customized appliances.

Abstract: This invention provides for an apparatus that controls a liquid level down-hole of a hydrocarbon producing well by physically monitoring the liquid level down-hole having a down-hole liquid level measurer and a signal device connected to the liquid level measurer that causes a pump to adjust its current liquid output based on the liquid level down-hole as measured by the down-hole liquid level measurer.

Abstract: Various embodiments herein each include at least one of systems, devices, methods, and software that provides on-demand, in process custom visualization. For example, some such embodiments provide such solutions that enable customers to view an augmented reality presentation, which may be a three-dimensional or holographic view, of a product with any selected options at the discretion of the customer. One such embodiment in the form of a method includes presenting, via a visual output of an augmented reality device, a selectable menu of customizable items and customizable features thereof and receiving a selection of a customizable item and at least one customizable feature. This method further includes presenting, via the visual output of the augmented reality device, a view of the selected customizable item and each selected at least one customizable feature as the input is received.

Abstract: A method is provided for preparing a hair dye color mixture. The method includes: accessing a control system having at least a processor, a memory, and user input controls, the memory configured to store ingredients of a hair dye color mixture, each ingredient of the hair dye color mixture being from an initial product brand; receiving user input from the user input controls to change one or more ingredients of the hair dye color mixture from the initial product brand to one or more subsequent product brands; matching the color of the hair dye color mixture made from one or more ingredients of the initial product brand using one or more ingredients of the one or more subsequent product brands, in response to the user input; and displaying the ingredients of the hair dye color mixture in the one or more subsequent product brands on a display.

Abstract: Systems and methods are directed to efficient management of processor resources, particularly General Purpose Registers (GPRs), for example to minimize pipeline flushes prevent deadlocks by counting GPRs instead of allocating them to specific blocks of code. Blocks of code are allowed to execute if the Free GPRs count is adequate. The method contemplates counting the number of Register Writers in blocks of code which will write to GPRs which are in process of executing, and counting the GPRs which are available instead of merely allocating them to dedicated use by a block of code, or an instruction in a block of code. Because blocks do not run if there is not enough GPRs available for the block, deadlocks and pipeline flushes due to lack of resources can be minimized.

Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry.

Abstract: Caching instruction block header data in block architecture processor-based systems is disclosed. In one aspect, a computer processor device, based on a block architecture, provides an instruction block header cache dedicated to caching instruction block header data. Upon a subsequent fetch of an instruction block, cached instruction block header data may be retrieved from the instruction block header cache (if present) and used to optimize processing of the instruction block. In some aspects, the instruction block header data may include a microarchitectural block header (MBH) generated upon the first decoding of the instruction block by an MBH generation circuit. The MBH may contain static or dynamic information about the instructions within the instruction block. As non-limiting examples, the information may include data relating to register reads and writes, load and store operations, branch information, predicate information, special instructions, and/or serial execution preferences.

Abstract: A chute control assembly for a snow thrower having a housing, handle, and a chute includes a control mechanism, a connecting mechanism, and a guide mechanism. The control mechanism includes an actuator mechanism that allows an operator to manually control the orientation of the chute from a position spaced apart from the chute. The connecting mechanism transfers rotation of the actuator mechanism to the guide mechanism. The guide mechanism is attached to the chute and rotates and adjust the orientation of the chute in response to rotation of the actuator mechanism in order to change the direction that snow is thrown from the snow thrower.

Abstract: A method is provided for preparing a hair dye color mixture. The method includes: providing a control system having at least a memory, input controls, and a display; storing in the memory at least one formula, the formula including one or more colorants and/or dye blending materials, and wherein each colorant and/or blending material is separately assigned to an initial product brand; receiving input from the input controls to change a colorant and/or blending material from the initial product brand to one or more subsequent product brands, and wherein the control system recalculates components of the formula using the one or more subsequent product brands in response to receiving input from the input controls; and matching the color of the hair dye color mixture made from colorants and/or dye blending materials of the initial product brand using colorants and/or dye blending materials of the one or more subsequent product brands, in response to the input.