Patents by Inventor Michael Xiaonan Wang

Michael Xiaonan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7426710
    Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength. On-chip clock distribution is an important application where cell libraries of the invention can provide significant advantages.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: September 16, 2008
    Assignee: VeriSilicon Holdings, Co. Ltd.
    Inventors: Xiaonan Zhang, Michael Xiaonan Wang
  • Patent number: 7254802
    Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: August 7, 2007
    Assignee: VeriSilicon Holdings, Co. Ltd.
    Inventors: Xiaonan Zhang, Michael Xiaonan Wang
  • Patent number: 7114134
    Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: September 26, 2006
    Assignee: Veri Silicon Holdings, Co. LTD
    Inventors: Xiaonan Zhang, Michael Xiaonan Wang