Abstract: Systems, apparatus, methods, and non-transitory media for programmatically grouping consumers are discussed herein. Some embodiments may include a system configured to provide to shared promotion redemptions. The system may include a merchant device with processing circuitry configured to associate multiple consumer accounts with a point-of-sale order. Based on receiving redemption data from a consumer device associated with one of the consumer accounts, the system may be further configured to allow the consumer device to share a selected promotion. For example, the system may determine payment share amounts for each consumer account based on a transaction price of the point-of-sale order and the redemption value of the promotion selected for shared redemption.

Abstract: An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

Abstract: An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

Abstract: Enhanced Platform Based SOC Design Including Extended Peripheral Selection and Automated IP Customization Facilitation An EDA tool suite is provided to facilitate SOC design in a platform based manner, by first facilitating the selection of a compute engine, then supporting peripheral devices layered upon the compute engine in at least a single peripheral layer. In various embodiments, the EDA tool suite includes pre-processing functions to identify connectivity of an IP component, and automatic creation of a user interface to facilitate provision of customization inputs. The EDA tool suite further includes bus bridges bridging a plurality of bus architecture pairs, and component selection facilities that automatically provides an expanded list of components for selection, including components connectable to a selected compute engine by way of a pre-provided bus bridge, responsive to the selection of the compute engine.

Abstract: An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment, the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.