Abstract: A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.

Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

Abstract: Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.

Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.

Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

Abstract: Methods and systems are disclosed for executing a collaborative task in a shader system. Techniques disclosed include receiving, by the system, input data and computing instructions associated with the collaborative task, as well as a configuration setting, causing the system to operate in a takeover mode. The system then launches, exclusively in one workgroup processor, a workgroup including wavefronts configured to execute the collaborative task.

Abstract: Methods and systems are disclosed for executing operations on single-instruction-multiple-data (SIMD) units. Techniques disclosed perform a dot product operation on input data during one computer cycle, including convolving the input data, generating intermediate data, and applying one or more transitional operations to the intermediate data to generate output data. Aspects described, wherein the input data is an input to a layer of a convolutional neural network and the generated output data is the output of the layer.

Abstract: A circuit including a multiplexer and a comparator. The multiplexer has one input coupled to a portion of an odd result address bus and another input coupled to a portion of an even result address bus. The control input of the multiplexer is coupled to a least significant bit line of a source address bus. The output of the multiplexer is coupled to one input of the comparator, and the other input is coupled to a portion of the source address bus.

Abstract: The invention comprises in several embodiments a pipeline and a method of operating the pipeline. The pipeline comprises first and second stages each having an output. The first stage is located earlier in the pipeline than the second stage. A first isolation device has an input coupled to the output of the first stage. The first isolation device is for storing data received from the first stage. A second isolation device has an input coupled to the output of the second stage. The second isolation device is for storing data received from the second stage. A stall control is for sending a signal to the first and second isolation devices. The signal is to stall the isolation devices. At least one delay element is connected between the stall control and the second isolation device and is to delay receipt of the signal by the second isolation device.