Abstract: A system for measuring a length of a work piece including a leveling fixture disposed at a first end of the work piece and a range target disposed at a second end. The leveling fixture includes a precision stop abutting against the first end and range finders configured to be substantially aligned with the first end. The range target includes a target stop abutting against the second end and a vertical portion substantially aligned with the second end when the target stop abuts the second end. The range finders are each configured to take measurements between the range finders and the vertical portion of the range target so as to provide a measurement of the length of the work piece.

Abstract: A system for measuring a length of a work piece including a leveling fixture disposed at a first end of the work piece and a range target disposed at a second end. The leveling fixture includes a precision stop abutting against the first end and range finders configured to be substantially aligned with the first end. The range target includes a target stop abutting against the second end and a vertical portion substantially aligned with the second end when the target stop abuts the second end. The range finders are each configured to take measurements between the range finders and the vertical portion of the range target so as to provide a measurement of the length of the work piece.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: To verify hardware, identical input values are provided to the first device under test and to the second device under test where the second device under test is logically identical to the first device under test. Output values of the first device under test and the second device under test are compared where both first output values from the first device under test are deterministically predictable from the identical input values and where second output values from the second device under test are deterministically predictable from the identical input values. Differences in the first output values from the second output values indicate incorrect operation.

Abstract: A method for verification of hardware uses self-equivalence to leverage automated abstractions where data path elements are identical in two designs. Equivalence is used between a qualified design and an independent reference.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.