Patents by Inventor Michael Zhai

Michael Zhai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DOSAGE REGIMES FOR ANTI-CD73 AND ANTI-ENTPD2 ANTIBODIES AND USES THEREOF
    Publication number: 20240141060
    Abstract: The invention generally relates to dosage regimes of anti-Cluster of Differentiation 73 (CD73) antibodies and/or anti-ectoenzyme ectonucleoside triphosphate diphosphohydrolase 2 (ENTPD2) antibodies, used in methods of treatment of cancer in a subject, as well as dosage regimes of anti-CD73 antibodies for use in treating cancer. The invention further generally relates to dosage regimes of combinations of agents, such as combinations comprising anti-CD73 antibodies and/or anti-ENTPD2 antibodies and at least one or more of a PD-1 inhibitor, and an adenosine A2AR antagonist.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 2, 2024
    Inventors: Juan Gonzalez-Maffe, Randi Ellen Isaacs, Jaeyeon Kim, Lisa Nardi, Javier Alberto Otero, Nehal Parikh, Michael John Roy, Kulandayan Kasi Subramanian, Tingting Zhai
  • STAGGERED DUAL-SIDE MULTI-CHIP INTERCONNECT
    Publication number: 20230411365
    Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 21, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Staggered dual-side multi-chip interconnect
    Patent number: 11798923
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: NVIDIA CORP.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Staggered Dual-Side Multi-Chip Interconnect
    Publication number: 20230197696
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma