Abstract: The present disclosure relates to semiconductor structures and, more particularly, to buried interconnect structures and methods of manufacture. The structure includes: a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; and at least one buried interconnect structure in the semiconductor substrate and crossing the trench isolation structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to quantum dot structures and methods of manufacture. The structure includes: a plurality of barrier gates; a plurality of spin qubit gates interdigitated with the plurality of barrier gates; and access gates on opposing sides of the plurality of barrier gates.

Abstract: Embodiments of the disclosure provide a structure with a guard ring between the terminals of a single photon avalanche diode photodetector (SPAD), and related methods. A structure according to the disclosure includes a SPAD with an anode within a doped well and a cathode within the doped well. A guard ring includes a semiconductor material within the doped well. The semiconductor material and the doped well have opposite doping polarities.

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Abstract: The present disclosure generally relates to a system for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to a system including a driver circuit, a bias generator, and a light sensor. The driver circuit has at least one transistor including a back gate and a front gate. The bias generator is connected to the back gate of the transistor. The light sensor is connected to the bias generator. The system is capable of adjusting the brightness of a display unit to adapt to the brightness of an ambient light.

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

Abstract: The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.

Abstract: A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.