Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.

Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.