Abstract: An arrangement (100) has a low voltage circuit (196') on a first doped well (110) and a high voltage circuit (197') on a second doped well (120) integrated into a common semiconductor substrate (105). The first well (110) laterally extends along a surface (106) of the substrate (105) to provide a voltage drop (.vertline.V.sub.LARGE .vertline.) between a first end (111) and a second end (112) so that potential differences between the circuits (196', 197') are substantially isolated. The low voltage circuit (196') controls a current from the second end (112) to provide a variable potential (by .vertline.V.sub.SMALL .vertline.) at the second end (112) which is communicated to other parts (193') of the second circuit (197') by a connection (150). The wells (110, 120) are spaced to provide isolation for potential magnitude changes between the second end (112) of the first well (110) and the second well (120) which are invoked by the first circuit (196').

Abstract: A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.