Patents by Inventor Michael Zwerg
Michael Zwerg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953969Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: GrantFiled: August 17, 2021Date of Patent: April 9, 2024Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 11847430Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: GrantFiled: November 8, 2021Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
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Publication number: 20230315142Abstract: An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.Type: ApplicationFiled: March 31, 2023Publication date: October 5, 2023Inventor: Michael Zwerg
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Publication number: 20230315661Abstract: An example apparatus includes a first memory configured to store a table, and a direct memory access controller coupled to the first memory and including a second memory local to the direct memory access controller, the direct memory access controller configured to read a first set of data from a first location in the table, wherein the first set of data includes an address, write the first set of data from the table to the second memory of the direct memory access controller, read a second set of data from a second location in the table, the second location different than the first location, and write the second set of data to a third location in the first memory, wherein the third location corresponds to the address of the first set of data.Type: ApplicationFiled: March 31, 2023Publication date: October 5, 2023Inventor: Michael Zwerg
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Patent number: 11393971Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: GrantFiled: November 27, 2018Date of Patent: July 19, 2022Assignee: Texas Instruments IncorporatedInventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20220057996Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
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Publication number: 20210389174Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Patent number: 11200030Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: GrantFiled: December 11, 2019Date of Patent: December 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
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Publication number: 20210373647Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Inventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 11132050Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: GrantFiled: June 25, 2019Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 11105676Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: GrantFiled: November 14, 2018Date of Patent: August 31, 2021Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Patent number: 10873020Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.Type: GrantFiled: August 8, 2017Date of Patent: December 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wei-Yan Shih, Sudhanshu Khanna, Michael Zwerg, Juergen Luebbe, Gregory Allen North, Steven C. Bartling, Leah Trautmann, Scott Robert Summerfelt
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Publication number: 20200168786Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20200117425Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
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Patent number: 10545728Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: GrantFiled: November 30, 2017Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
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Publication number: 20190377404Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: ApplicationFiled: June 25, 2019Publication date: December 12, 2019Inventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
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Patent number: 10331203Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: GrantFiled: February 5, 2016Date of Patent: June 25, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
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Publication number: 20190162590Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: November 14, 2018Publication date: May 30, 2019Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20190051812Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.Type: ApplicationFiled: August 8, 2017Publication date: February 14, 2019Inventors: Wei-Yan Shih, Sudhanshu Khanna, Michael Zwerg, Juergen Luebbe, Gregory Allen North, Steven C. Bartling, Leah Trautmann, Scott Robert Summerfelt
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Publication number: 20190034169Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: ApplicationFiled: November 30, 2017Publication date: January 31, 2019Inventors: Sudhanshu KHANNA, Hao MENG, Michael ZWERG, Christy Leigh SHE, Steven Craig BARTLING