Abstract: A signal generator and a method which provides a source signal with a coherent phase at arbitrary times is presented. There is provided a signal generator for generating a source signal based on a reference signal. The signal generator has a phase setting circuit with a memory circuit operable between a plurality of states. The memory circuit has a phase setting input adapted to receive a phase setting value to set the memory circuit to a known state. The signal generator is adapted to load the phase setting value at a specific time to control a phase of the source signal.

Abstract: A low power signal generator and a method for generating at least one source signal based on a reference signal having a reference frequency is presented. The signal generator has a divider circuit having a resonant frequency. The generator has an adjuster adapted to adjust the resonant frequency. The divider circuit has an input to receive the reference signal and an output for providing the source signal. The divider circuit is adapted to divide the reference frequency of the reference signal by a coefficient, such that the source signal has a source frequency that is less than the reference frequency.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.

Abstract: A device for true random number generation is disclosed. The device comprises an antenna and an analog processing unit for analog processing of a signal received from the antenna. An analog to digital (AD) converter is used for converting an analog signal generated by the analog processing unit into a digital signal. An isolation means is applied for temporarily isolating the antenna from the analog processing unit and the AD converter to generate a noise signal. A sampling means is used for sampling output values generated by the AD converter when the antenna is isolated from the analog processing unit and the AD converter. A digital processing unit is used for processing the sampled output values generated by the AD converter. The digital processing unit is configured to generate a random number based on one or more of the output values generated by the AD converter.

Abstract: An integrated circuit, comprising a single-ended pin for transmitting and/or receiving an RF signal. A first matching network is configured to match an impedance of the RF signal. A second matching network is configured to match an impedance of an on-chip differential circuit. A third matching network is configured to match an impedance of an on-chip single-ended circuit, wherein the third matching network is connectable to the first matching network. A transformer is connected or connectable to the second matching network and to the first matching network. Switches control an operating mode of the integrated circuit The second matching network is connected with the first matching network via the transformer, or the third matching network is connected with the first matching network.

Abstract: A device for true random number generation is disclosed. The device comprises an antenna and an analog processing unit for analog processing of a signal received from the antenna. An analog to digital (AD) converter is used for converting an analog signal generated by the analog processing unit into a digital signal. An isolation means is applied for temporarily isolating the antenna from the analog processing unit and the AD converter to generate a noise signal. A sampling means is used for sampling output values generated by the AD converter when the antenna is isolated from the analog processing unit and the AD converter. A digital processing unit is used for processing the sampled output values generated by the AD converter. The digital processing unit is configured to generate a random number based on one or more of the output values generated by the AD converter.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: An integrated circuit, comprising a single-ended pin for transmitting and/or receiving an RF signal. A first matching network is configured to match an impedance of the RF signal. A second matching network is configured to match an impedance of an on-chip differential circuit. A third matching network is configured to match an impedance of an on-chip single-ended circuit, wherein the third matching network is connectable to the first matching network. A transformer is connected or connectable to the second matching network and to the first matching network. Switches control an operating mode of the integrated circuit The second matching network is connected with the first matching network via the transformer, or the third matching network is connected with the first matching network.