Patents by Inventor Michal J Rewienski

Michal J Rewienski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8091052
    Abstract: A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 3, 2012
    Assignee: Synopsys, Inc.
    Inventors: Michal J Rewienski, Kevin J Kerns
  • Publication number: 20090113356
    Abstract: A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of the present invention also detect and optimize parasitic capacitors to facilitate formation of the ideal sub-arrays.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Applicant: Synopsys, Inc.
    Inventors: Michal J. Rewienski, Kevin J. Kerns