Patents by Inventor Michal MLECZKO

Michal MLECZKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer
    Patent number: 11984506
    Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Vishal Tiwari, Rishabh Mehandru, Dan S. Lavric, Michal Mleczko, Szuya S. Liao
  • Pathogen Clearance System and Method
    Publication number: 20230335297
    Abstract: The present embodiments relate to pathogen clearance. Subject matter of the present embodiments are computer-implemented methods, computer systems and computer-readable storage media for predicting the performance of pathogen clearance processes.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 19, 2023
    Inventors: Shyam PANJWANI, Konstantinos SPETSIERIS, Michal MLECZKO, Wensheng WANG, June Zou, Mohammad ANWARUZZAMAN, Oliver HESSE, Roger CANALES, JIARONG CUI, Shengjiang LIU
  • FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYER AND HAVING A GATE STRESSOR LAYER
    Publication number: 20210408282
    Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Inventors: Vishal TIWARI, Rishabh MEHANDRU, Dan S. LAVRIC, Michal MLECZKO, Szuya S. LIAO