Patents by Inventor Michal Rimon
Michal Rimon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11188304Abstract: Validating microprocessor instruction execution by receiving a floating-point exception selection, receiving a validation method selection, generating validation data according to the floating-point exception selection and the validation method selection by randomly generating a first tensor element value and randomly generating a second tensor element value according to the first tensor element value and the floating-point exception selection, and executing a floating-point computation according to the validation data.Type: GrantFiled: July 1, 2020Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Gal Ashour, Oz Dov Hershkovitz, Michal Rimon, Karen Holtz, Silvia Melitta Mueller, Avishai Moshe Fedida
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Patent number: 9734033Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.Type: GrantFiled: December 8, 2014Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
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Patent number: 9720793Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.Type: GrantFiled: September 20, 2015Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
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Publication number: 20160162380Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.Type: ApplicationFiled: December 8, 2014Publication date: June 9, 2016Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
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Publication number: 20160162381Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.Type: ApplicationFiled: September 20, 2015Publication date: June 9, 2016Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
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Patent number: 9208451Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.Type: GrantFiled: February 5, 2014Date of Patent: December 8, 2015Assignee: GlobalFoundries Inc.Inventors: Yoav Katz, Michal Rimon, Elad Yom-Tov, Avi Ziv
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Patent number: 8938646Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.Type: GrantFiled: October 24, 2012Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Laurent Fournier, Anatoly Koyfman, Michal Rimon, Avi Ziv
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Patent number: 8930759Abstract: A method, apparatus and product for generating elements based on generation streams. The method comprises: obtaining one or more generation streams, wherein the streams comprise elements, wherein each element is a formal specification of an operation that stimulates a system, wherein based on each of the generation streams one or more alternative stimuli for the system can be generated, which stimuli comprises operations according to the elements; and generating a stimuli in accordance with the one or more generation streams, wherein the stimuli comprises at least one hybrid operation, wherein the hybrid operation complies simultaneously with two or more elements of the one or more generation stream, whereby the stimuli is comprised of a number of operations that is smaller than a sum of the numbers of elements of the one or more generation streams.Type: GrantFiled: April 2, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Yoav Katz, Michal Rimon, Avi Ziv
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Patent number: 8826075Abstract: A method, apparatus and product. The method comprising automatically determining an abstract CSP based on a formally defined problem having interconnected sub-problems, wherein the abstract CSP corresponds to the problem, wherein the abstract CSP has a reduced complexity in comparison to a CSP representing the problem, wherein the abstract CSP captures the interconnection between the sub-problems and reduces the details of each sub-problem, wherein the abstract CSP comprises constraints over variables, wherein each variable having an associated domain; and repeatedly: (1) propagating constraints of the abstract CSP to reduce domains of the abstract CSP; (2) selecting a sub-problem to solve; (3) solving the sub-problem; and (4) updating the abstract CSP with values in accordance with the solution of the sub-problem. Whereby, a solution to the formally defined problem is determined based on the solutions to the sub-problems.Type: GrantFiled: February 20, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Yoav Katz, Michal Rimon, Avi Ziv
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Publication number: 20140156572Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.Type: ApplicationFiled: February 5, 2014Publication date: June 5, 2014Applicant: International Business Machines CorporationInventors: YOAV KATZ, MICHAL RIMON, ELAD YOM-TOV, AVI ZIV
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Publication number: 20140115396Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.Type: ApplicationFiled: October 24, 2012Publication date: April 24, 2014Inventors: Laurent Fournier, Anatoly Koyfman, Michal Rimon, Avi Ziv
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Patent number: 8683282Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.Type: GrantFiled: March 1, 2011Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Yoav Avraham Katz, Michal Rimon, Elad Yom-Tov, Avi Ziv
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Patent number: 8589892Abstract: A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.Type: GrantFiled: November 21, 2010Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Laurent Fournier, Anatoly Albert Koyfman, Michal Rimon
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Publication number: 20130262932Abstract: A method, apparatus and product for generating elements based on generation streams. The method comprises: obtaining one or more generation streams, wherein the streams comprise elements, wherein each element is a formal specification of an operation that stimulates a system, wherein based on each of the generation streams one or more alternative stimuli for the system can be generated, which stimuli comprises operations according to the elements; and generating a stimuli in accordance with the one or more generation streams, wherein the stimuli comprises at least one hybrid operation, wherein the hybrid operation complies simultaneously with two or more elements of the one or more generation stream, whereby the stimuli is comprised of a number of operations that is smaller than a sum of the numbers of elements of the one or more generation streams.Type: ApplicationFiled: April 2, 2012Publication date: October 3, 2013Applicant: International Business Machines CorporationInventors: Yoav Katz, Michal Rimon, Avi Ziv
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Publication number: 20130219215Abstract: A method, apparatus and product. The method comprising automatically determining an abstract CSP based on a formally defined problem having interconnected sub-problems, wherein the abstract CSP corresponds to the problem, wherein the abstract CSP has a reduced complexity in comparison to a CSP representing the problem, wherein the abstract CSP captures the interconnection between the sub-problems and reduces the details of each sub-problem, wherein the abstract CSP comprises constraints over variables, wherein each variable having an associated domain; and repeatedly: (1) propagating constraints of the abstract CSP to reduce domains of the abstract CSP; (2) selecting a sub-problem to solve; (3) solving the sub-problem; and (4) updating the abstract CSP with values in accordance with the solution of the sub-problem. Whereby, a solution to the formally defined problem is determined based on the solutions to the sub-problems.Type: ApplicationFiled: February 20, 2012Publication date: August 22, 2013Applicant: International Business Machines CorporationInventors: Yoav Katz, Michal Rimon, Avi Ziv
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Publication number: 20120226952Abstract: a computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.Type: ApplicationFiled: March 1, 2011Publication date: September 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yoav Avraham Katz, Michal Rimon, Elad Yom-Tov, Avi Ziv
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Publication number: 20120131386Abstract: A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.Type: ApplicationFiled: November 21, 2010Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Lurent Fournier, Anatoly Koyfman, Michal Rimon
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Publication number: 20110320784Abstract: A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eli Almog, Christopher A. Krygowski, Yugi Morimoto, Michal Rimon
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Patent number: 7133816Abstract: A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.Type: GrantFiled: November 4, 2002Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik
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Publication number: 20040088600Abstract: A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.Type: ApplicationFiled: November 4, 2002Publication date: May 6, 2004Applicant: International Business Machines CorporationInventors: Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik