Patents by Inventor MICHAL SILBERMINTZ

MICHAL SILBERMINTZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836384
    Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Gadi Vishne, Michal Silbermintz, Danny Berler
  • Publication number: 20230289093
    Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Gadi VISHNE, Michal SILBERMINTZ, Danny BERLER
  • Patent number: 10929224
    Abstract: A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avi Klein, Eran Sharon, Gadi Vishne, Igor Genshaft, Marina Frid, Michal Silbermintz
  • Patent number: 10901655
    Abstract: A non-volatile memory die includes a plurality of non-volatile memory cells and die control circuitry. The die control circuitry is configured to respond to a received command to access the plurality of non-volatile memory cells by sending a response indicated by the received command together with die variable information. The die variable information includes information not indicated by the received command.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Gadi Vishne, Michal Silbermintz
  • Publication number: 20200401477
    Abstract: A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Avi Klein, Eran Sharon, Gadi Vishne, Igor Genshaft, Marina Frid, Michal Silbermintz
  • Patent number: 10795604
    Abstract: The disclosure relates in some aspects to reporting the amount of available physical storage space of a non-volatile memory (NVM) array. A device including an NVM array may send reports regarding the amount of available physical storage space in the non-volatile memory device to a host device or some other suitable apparatus. The amount of available physical storage space takes into account whether any of the physical address blocks of the NVM array have been designated as worn-out. The host device (or other suitable apparatus) may send a report to a user when the amount of available physical storage space is relatively low.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 6, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michal Silbermintz, David Haliva, Gadi Vishne
  • Publication number: 20200104070
    Abstract: A non-volatile memory die includes a plurality of non-volatile memory cells and die control circuitry. The die control circuitry is configured to respond to a received command to access the plurality of non-volatile memory cells by sending a response indicated by the received command together with die variable information. The die variable information includes information not indicated by the received command.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Gadi Vishne, Michal Silbermintz
  • Publication number: 20200026457
    Abstract: The disclosure relates in some aspects to reporting the amount of available physical storage space of a non-volatile memory (NVM) array. A device including an NVM array may send reports regarding the amount of available physical storage space in the non-volatile memory device to a host device or some other suitable apparatus. The amount of available physical storage space takes into account whether any of the physical address blocks of the NVM array have been designated as worn-out. The host device (or other suitable apparatus) may send a report to a user when the amount of available physical storage space is relatively low.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: Michal Silbermintz, David Haliva, Gadi Vishne
  • Patent number: 10409570
    Abstract: A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. The builder module to build executable applications for the target processor based on a set of instructions. The call graph generator to create a first call graph that indicates a stack usage for each call path of the executable applications. If a first executable application built by the builder module includes a call path that exceeds a stack size constraint of the target processor, the builder module to optimize only functions within the call path that exceeds the stack size constraint in response to the request from the evaluation monitor, and to build a second executable application based on the set of instructions. The second executable application is optimized for stack memory usage of the target processor.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 10, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michal Silbermintz, John Russo
  • Patent number: 10412046
    Abstract: There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. It is thus possible to continue using look-up tables while updating process is being carried out for some or all of the table entries. The solution provides benefits for systems that are limited in space and cost, by use of minimal memory thanks to the storing of small shadowed data instead of full shadowed table.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 10, 2019
    Assignee: NXP USA, Inc.
    Inventors: Avishay Moscovici, Michal Silbermintz
  • Publication number: 20180107465
    Abstract: A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. The builder module to build executable applications for the target processor based on a set of instructions. The call graph generator to create a first call graph that indicates a stack usage for each call path of the executable applications. If a first executable application built by the builder module includes a call path that exceeds a stack size constraint of the target processor, the builder module to optimize only functions within the call path that exceeds the stack size constraint in response to the request from the evaluation monitor, and to build a second executable application based on the set of instructions. The second executable application is optimized for stack memory usage of the target processor.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 19, 2018
    Inventors: Michal Silbermintz, John Russo
  • Publication number: 20150363448
    Abstract: There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. It is thus possible to continue using look-up tables while updating process is being carried out for some or all of the table entries. The solution provides benefits for systems that are limited in space and cost, by use of minimal memory thanks to the storing of small shadowed data instead of full shadowed table.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: AVISHAY MOSCOVICI, MICHAL SILBERMINTZ