Abstract: A constant phase crossbar switch system which avoids phase discontinuities at the outputs of the crossbar switch. The crossbar switch system includes input logic, a crossbar switch, output logic and a phase locked loop. The phase locked loop is used to generate a high speed internal clock from a system clock. High speed serial data streams transmitted at the internal clock frequency are received from corresponding transmitters and are coupled to the input logic. The input logic generates multiple versions of each serial data stream, one of the versions being undelayed and the other versions delayed by some fraction of a bit time. State machines are employed to selects the version of the serial data stream which results in the data stream data window being generally centered with respect to the high speed internal clock. The selected version of the data stream is employed as the active input to the crossbar switch.