Abstract: A multiprocessor system for processing digital data includes a plurality of P buses and a plurality of at most P(P-1)/2 processor stations. Each station is connected to a pair of buses. The pair of buses to which a station is connected is different for each station. Each station is directly connected to 2(P-2) stations, and indirectly connected through a single relay station to at most (P-2) (P-3)/2 stations. The buses have addresses 1 to P and each station is given one complete address formed by the concatenation in any order of the addresses of the two buses to which it is connected and two incomplete addresses formed by the address of any of the two buses to which it is connected. When detecting its complete address, a station behaves as an addressee station and when detecting one of its two incomplete addresses, a station behaves as a relay station.