Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

Abstract: A unitary housing for an extended-format releasable plug-in card (15). The housing comprises a first block (12) adapted to the standard plug-in card format and designed to contain the standardized portion of the card (15) inserted into the slot of a microcomputer, as well as a second block (16). The housing is characterized in that the second block (16) can receive at least the extension (Z.sub.2) of the card (15), and includes flanges (18) positionable between the side edges of the card (15) and those of the first block (12). The flanges (18) enable the first and second blocks (12, 16) to be rigidly connected so that they are inseparable and the whole housing thereafter forms a single block. Said housing is useful for mechanically protecting extended-format PCMCIA electronics.