Abstract: A performance evaluation apparatus is provided for annotating by priority level a DSP intermediate representation (DIR) of an application source code. The DIR includes nodes, leaf nodes and heading nodes, wherein the heading nodes represent data ready operations. The apparatus includes a host computer, a target digital signal processor (DSP) compiler, and a DSP Intermediate Representation (DIR) annotation algorithm. The host computer includes processing circuitry, memory and a host compiler to use test sequences and generate dynamic information. The target digital signal processor compiler communicates with the processing circuitry. The DSP Intermediate Representation (DIR) annotation algorithm is implemented on the host processing circuitry and is operative to annotate application source code by giving priority to operations that allow more distant leaf nodes to be scheduled earlier. Accordingly, nodes with high priority levels are scheduled first, enabling extraction of target DSP pipeline parallelism.

Abstract: Disclosed are method and apparatus for synthesizing communication support based on communication types of an application. In the integrated circuit design method, an application schedule is provided for the application. The application schedule describes a plurality of units for performing specified tasks and one or more communication links between the specified tasks. After receiving the application schedule, the communication type is determined for each of the communication links in the application schedule as an asynchronous communication or a synchronous communication. Then, for each of the asynchronous communications, it is determined whether each asynchronous communication can be transformed into a semi-synchronous communication that uses an interrupt and a bus to transfer data. A communication support is synthesized for the semi-synchronous communications as synchronous communications by using the interrupt and the bus.

Abstract: An assembly code performance evaluation apparatus is provided which includes a host computer, a target digital signal processor (DSP) compiler, and a performance estimation program. The host computer includes processing circuitry, memory and a host compiler to use test sequences and generate dynamic information. The target digital signal processor compiler communicates with the processing circuitry. The performance estimation program is implemented on the host processing circuitry and is operative to annotate application source code and to generate an estimation of an optimized assembly code. A method is also provided.

Abstract: The invention relates to a device for opening bivalve shellfish, particularly oysters. It comprises: a base (1) consisting of a longitudinal cradle having a first end (1a) comprising a stop (10) and a second end (1b) comprising first reaction means, it being possible to place, a shellfish (2) between said two ends (1a, 1b) such that it bears against said stop (10); and perforating means (3) comprising a longitudinal blade (4) having a first pointed end and drive means for translational movement of said blade (4), said drive means comprising second reaction means (5a).