Patents by Inventor Michel Broyer

Michel Broyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9378175
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 28, 2016
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc
  • Patent number: 7809972
    Abstract: A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 5, 2010
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Pierre Michel Broyer
  • Patent number: 7676652
    Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 9, 2010
    Assignee: ARM Limited
    Inventors: Hedley James Francis, Frederic Claude Marie Piry, Pierre Michel Broyer
  • Publication number: 20090242753
    Abstract: The invention relates to a device for mass analysis of molecules comprising a quadripolar ion trap equipped with an inlet for injection of molecules to be analysed in ionised form and an outlet for ejection of the ions to be detected, comprising an electrode system for generating a three-dimensional quadripolar field, capable of trapping the molecules to be analysed in ionised form, as a function of their mass to charge (m/z) ratio in a trapping volume, said trap being coupled to a UV or visible laser beam ensuring dissociation of the molecules to be analysed, characterised in that the laser beam is introduced to the trap without passing via fibre optics via an opening made in one of the electrodes, separate from the inlet and the outlet and blocked tightly by a viewing window allowing the laser beam to pass through, the dimension of the viewing window being selected such that the laser beam covers the entire trapping volume, as well as a process for mass analysis, with laser beam dissociation.
    Type: Application
    Filed: December 15, 2005
    Publication date: October 1, 2009
    Applicants: UNIVERSITE CLAUDE BERNARD LYON 1, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.
    Inventors: Philippe Dogourd, Rodolphe Antoine, Michel Broyer, Francis Talbot
  • Publication number: 20080244299
    Abstract: The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Andrew David Tune, Pierre Michel Broyer
  • Publication number: 20080147921
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Application
    Filed: November 1, 2007
    Publication date: June 19, 2008
    Applicant: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc
  • Publication number: 20040059890
    Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 25, 2004
    Applicant: ARM LIMITED
    Inventors: Hedley James Francis, Frederic Claude Marie Piry, Pierre Michel Broyer